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    • 2. 发明授权
    • Method of making high density dielectric isolated gate MOS transistor
    • 制造高密度介质隔离栅MOS晶体管的方法
    • US4610078A
    • 1986-09-09
    • US684750
    • 1984-12-21
    • Naohiro MatsukawaHiroshi Nozawa
    • Naohiro MatsukawaHiroshi Nozawa
    • H01L29/78H01L21/28H01L21/336H01L21/308H01L21/265
    • H01L29/66575H01L21/28Y10S148/082
    • There is disclosed a method of manufacturing a semiconductor device comprising a step of forming an isolation film having a patterned hole on a major surface of a semiconductor substrate of a P conductivity type, the wall of the isolation film defining the patterned hole having a large step, a step of forming a polysilicon layer on the major surface of the structure, a step of forming a first interlaid SiO.sub.2 layer on the polysilicon layer, a step of patterning the SiO.sub.2 layer and polysilicon layer using reactive ion etching process, thereby forming on the region of the substrate a gate electrode and a first SiO.sub.2 film superposed thereon, the continuous side wall of the gate electrode and first SiO.sub.2 film having a large step, a step of implanting an impurity ion into the substrate using the first SiO.sub.2 film as a mask, thereby forming an impurity diffused region of an N conductivity type in the substrate, a step of forming a second interlaid SiO.sub.2 layer on the major surface of the structure, and a step of applying reactive ion etching to the second SiO.sub.2 layer, thereby forming a contact hole in the second SiO.sub.2 layer leading to the impurity diffused region, while leaving part of the second SiO.sub.2 layer on the side walls of said isolation film, gate electrode and first SiO.sub.2 film.
    • 公开了一种制造半导体器件的方法,包括在P导电型半导体衬底的主表面上形成具有图案化孔的隔离膜的步骤,隔离膜的壁限定具有大步长的图案化孔 在所述结构体的主表面上形成多晶硅层的工序,在所述多晶硅层上形成第一层叠SiO 2层的工序,使用反应离子蚀刻工序对所述SiO 2层和多晶硅层进行构图的工序, 所述基板的区域是栅电极和叠置在其上的第一SiO 2膜,所述栅电极的连续侧壁和具有大台阶的第一SiO 2膜,使用所述第一SiO 2膜作为掩模将杂质离子注入所述基板的步骤 ,从而在衬底中形成N导电类型的杂质扩散区域,在该结构的主表面上形成第二层间SiO 2层的步骤, 以及向第二SiO 2层施加反应离子蚀刻的步骤,从而在导致杂质扩散区域的第二SiO 2层中形成接触孔,同时在该隔离膜的侧壁上留下一部分第二SiO 2层,栅电极 和第一个SiO 2膜。
    • 6. 发明授权
    • Coding-decoding device and method for conversion of binary sequences
    • 用于转换二进制序列的编码解码装置和方法
    • US07039847B2
    • 2006-05-02
    • US10238984
    • 2002-09-09
    • Hiroshi NozawaShinzo KoyamaMasao TakayamaYoshikazu Fujimori
    • Hiroshi NozawaShinzo KoyamaMasao TakayamaYoshikazu Fujimori
    • G11C29/00
    • G11C7/1006
    • A coding-decoding device and a coding-decoding method that take less time for coding and decoding are provided while using less number of logic gates. A memory device 15 substantially stores b pieces of conversion logic equations produced with a conversion logic equation producing device 13. An operation device 17 has a programmable hardware logic circuit to constitute logics sequentially according to plural execution unit logic equations obtained by dividing b pieces of conversion logic equations stored in the memory device 15 into execution units for respective execution unit logic equations using the hardware logic circuit. Besides, the operation device 17 sequentially divides and calculates the second sentences from the first sentences according to the constituted logics. An output device 19 collects and outputs the second sentences calculated with the operation device 17.
    • 在使用较少数量的逻辑门的同时,提供了编码解码装置和编码解码方法,其中编码解码时间较短。 存储器装置15基本上存储由转换逻辑方程产生装置13产生的b个转换逻辑方程式。 操作装置17具有可编程硬件逻辑电路,以根据通过使用硬件逻辑电路将存储在存储器件15中的b个转换逻辑方程分成执行单元逻辑方程而获得的多个执行单元逻辑方程来顺序地构成逻辑 。 此外,操作装置17根据构成的逻辑顺序地分割和计算来自第一句子的第二句子。 输出装置19收集并输出用操作装置17计算的第二句子。
    • 8. 发明授权
    • Memory device with processing function
    • 具有处理功能的内存设备
    • US6055176A
    • 2000-04-25
    • US268972
    • 1999-03-16
    • Keikichi TamaruHiroshi NozawaYoshiro FujiiAkira Kamisawa
    • Keikichi TamaruHiroshi NozawaYoshiro FujiiAkira Kamisawa
    • G11C14/00G11C7/00G11C7/10G11C11/22
    • G11C7/1006G11C11/22
    • It is an object of the present invention to provide a memory device with processing function using less transistors, and capable of operating with simple operation and allows its operation with less trouble. Each of W cells 34 includes a ferroelectric capacitor CF. One end 40 of the ferroelectric capacitor CF is connected to one of data lines D through a transistor T1. The one end 40 of the ferroelectric capacitor CF is connected to an inner data line MW through a transistor T2. The structure of the Q cells 36 is almost the same as that of the W cells 34. Both readout/writing operations of data from the outside of the device are performed by using the data line D. Data read out from both the W cell 34 and the Q cell 36 is sent to the adder 28 and added thereby, and the resultant data of the addition is written to the Q cell 36 through a buffer circuit 32. The memory device with processing function can be realized with a simple structure by using ferroelectric capacitors CF.
    • 本发明的目的是提供一种具有使用较少晶体管的处理功能的存储器件,并且能够以简单的操作进行操作并允许其操作更少的麻烦。 W单元34中的每一个包括铁电电容器CF。 铁电电容器CF的一端40通过晶体管T1连接到数据线D之一。 铁电电容器CF的一端40通过晶体管T2连接到内部数据线MW。 Q单元36的结构与W单元34的结构几乎相同。通过使用数据线D来执行来自设备外部的数据的读/写操作。从W单元34读出的数据 并且Q单元36被发送到加法器28并由此相加,并且所得到的相加数据通过缓冲电路32写入Q单元36.具有处理功能的存储器件可以通过使用简单的结构来实现 铁电电容器CF
    • 9. 发明授权
    • Method of manufacturing a solid state image sensing device
    • 制造固体摄像装置的方法
    • US5264374A
    • 1993-11-23
    • US694768
    • 1991-05-02
    • Kazunari WatanabeHiroshi Nozawa
    • Kazunari WatanabeHiroshi Nozawa
    • H01L27/148H01L21/339
    • H01L27/14831
    • In a solid state image sensing device comprising: a semiconductor substrate; a photosensitive pixel area disposed on the semiconductor substrate for generating signal charges in response to incident light and storing the signal charges; a charge transfer area disposed adjacent to the photosensitive pixel area for transferring the signal charges stored in the photosensitive pixel area; and a transfer electrode provided above the charge transfer area, the solid state image sensing device comprises: a high melting temperature metal layer composed of molybdenum silicide MoSi formed above the transfer electrode and an insulating layer having ample thickness formed between the high melting temperature metal layer and the transfer electrode. The light shielding efficiency can be improved and occurrence of a smear phenomenon can be prevented in the resulting device.
    • 一种固体摄像装置,包括:半导体衬底; 设置在所述半导体衬底上的光敏像素区域,用于响应于入射光产生信号电荷并存储所述信号电荷; 与光敏像素区域相邻设置的用于传送存储在感光像素区域中的信号电荷的电荷转移区域; 以及设置在所述电荷转移区域之上的转移电极,所述固态图像感测装置包括:形成在所述转移电极上方的由硅化钼MoSi构成的高熔点金属层和在所述高熔点金属层之间形成的具有足够厚度的绝缘层 和转印电极。 可以提高遮光效率,并且可以防止在所得到的装置中产生污迹现象。
    • 10. 发明申请
    • POLYPROPYLENE RESIN COMPOSITION AND FILM THEREOF
    • 聚丙烯树脂组合物及其薄膜
    • US20100204369A1
    • 2010-08-12
    • US12667593
    • 2008-07-03
    • Hiroshi Nozawa
    • Hiroshi Nozawa
    • C08K5/04
    • C08L23/14C08J5/18C08J2323/14C08K5/14C08L23/04C08L23/142C08L2666/06
    • A polypropylene resin composition that has a melt flow rate of 1.5 (g/10 minutes) or more and is obtainable by melt-kneading 94 to 98 parts by weight of (A) a propylene copolymer that comprises a polymer portion being obtainable by polymerizing monomers containing propylene as the major component and having an intrinsic viscosity of 2.0 (dL/g) or more and a copolymer portion being obtainable by copolymerizing propylene and ethylene, 2 to 6 parts by weight of (B) an ethylene polymer having a density of 0.920 g/cm3 or more, and (C) an organic peroxide, provided that the total weight of the propylene copolymer (A) and the ethylene polymer (B).
    • 一种聚丙烯树脂组合物,其熔体流动速率为1.5(g / 10分钟)以上,通过熔融混炼得到94〜98重量份的(A)丙烯共聚物,该丙烯共聚物包含聚合物部分,该聚合物部分可通过聚合单体 含有丙烯作为主要成分,特性粘度为2.0(dL / g)以上,共聚物部分可通过丙烯与乙烯共聚获得,2〜6重量份的(B)密度为0.920的乙烯聚合物 g / cm 3以上,(C)有机过氧化物,前提是丙烯共聚物(A)和乙烯聚合物(B)的总重量。