专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06985023B2 Selective switching of a transistor's back gate potential 失效
标题翻译：选择性切换晶体管的背栅电位
公开(公告)号：US06985023B2
公开(公告)日：2006-01-10
申请号：US10768394
申请日：2004-01-30
申请人： Mami Kawabata , Masahiro Yoshihara , Eiichi Makino
发明人： Mami Kawabata , Masahiro Yoshihara , Eiichi Makino
IPC分类号： H03K19/0185 , H03K17/687
CPC分类号： G05F1/56 , G11C5/147 , H01L27/105
摘要： A semiconductor device comprises a first transistor and a potential generator circuit. The first transistor has a first conduction type first semiconductor region and a second conduction type second semiconductor region formed in the first semiconductor region. The first and second semiconductor regions are supplied with first and second prescribed potentials, respectively. The potential generator circuit generates the first prescribed potential. The potential generator circuit has a first power supply terminal supplied with a first power supply potential, a second power supply terminal supplied with a second power supply potential set to a higher potential than the first power supply potential, and an output terminal outputting the first prescribed potential. The potential generator circuit outputs the second power supply potential when the second power supply potential is higher than a predetermined potential, and the first power supply potential when the second power supply potential is lower than the predetermined potential.
摘要翻译：半导体器件包括第一晶体管和电位发生器电路。第一晶体管具有形成在第一半导体区域中的第一导电型第一半导体区域和第二导电型第二半导体区域。第一和第二半导体区域分别被提供第一和第二规定电位。电位发生器电路产生第一规定电位。电位发生器电路具有被提供有第一电源电位的第一电源端子，被提供有设置为比第一电源电位高的电位的第二电源电位的第二电源端子以及输出第一规定潜在。当第二电源电位高于预定电位时，电位发生器电路输出第二电源电位，而当第二电源电位低于预定电位时，该第一电源电位。

2. 发明授权

US07035153B2 Semiconductor memory device of bit line twist system 失效
标题翻译：位线扭转系统的半导体存储器件
公开(公告)号：US07035153B2
公开(公告)日：2006-04-25
申请号：US10978457
申请日：2004-11-02
申请人： Shintaro Hayashi , Manabu Satoh , Masahiro Yoshihara , Naoaki Kanagawa , Mami Kawabata
发明人： Shintaro Hayashi , Manabu Satoh , Masahiro Yoshihara , Naoaki Kanagawa , Mami Kawabata
IPC分类号： G11C29/00
CPC分类号： G11C29/816 , G11C7/1048 , G11C7/18 , G11C11/4097
摘要： A semiconductor memory device adopting a bit line twist system in which at least a part of bit lines are twisted, includes memory cell arrays each having a plurality of memory cells to store data, redundancy cell arrays each having a plurality of redundancy cells to replace a defective cell in the memory cell array, and a control circuit which performs control to invert a direction of the data. The device further includes an inversion circuit which inverts the direction of the data, in accordance with the control by the control circuit.
摘要翻译：采用位线扭转系统的半导体存储器件，其中位线的至少一部分被扭曲，包括每个具有多个存储单元以存储数据的存储单元阵列，每个具有多个冗余单元的冗余单元阵列以替代存储单元阵列中的有缺陷的单元，以及执行用于反转数据的方向的控制的控制电路。该装置还包括根据控制电路的控制来反转数据的方向的反相电路。

3. 发明申请

US20050141297A1 Semiconductor memory device of bit line twist system 失效
标题翻译：位线扭转系统的半导体存储器件
公开(公告)号：US20050141297A1
公开(公告)日：2005-06-30
申请号：US10978457
申请日：2004-11-02
申请人： Shintaro Hayashi , Manabu Satoh , Masahiro Yoshihara , Naoaki Kanagawa , Mami Kawabata
发明人： Shintaro Hayashi , Manabu Satoh , Masahiro Yoshihara , Naoaki Kanagawa , Mami Kawabata
IPC分类号： G11C29/04 , G11C7/10 , G11C7/18 , G11C11/401 , G11C11/4097 , G11C29/00 , G11C7/00
CPC分类号： G11C29/816 , G11C7/1048 , G11C7/18 , G11C11/4097
摘要： A semiconductor memory device adopting a bit line twist system in which at least a part of bit lines are twisted, includes memory cell arrays each having a plurality of memory cells to store data, redundancy cell arrays each having a plurality of redundancy cells to replace a defective cell in the memory cell array, and a control circuit which performs control to invert a direction of the data. The device further includes an inversion circuit which inverts the direction of the data, in accordance with the control by the control circuit.
摘要翻译：采用位线扭转系统的半导体存储器件，其中位线的至少一部分被扭曲，包括每个具有多个存储单元以存储数据的存储单元阵列，每个具有多个冗余单元的冗余单元阵列以替代存储单元阵列中的有缺陷的单元，以及执行用于反转数据的方向的控制的控制电路。该装置还包括根据控制电路的控制来反转数据的方向的反相电路。

4. 发明授权

US08923074B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08923074B2
公开(公告)日：2014-12-30
申请号：US13432465
申请日：2012-03-28
申请人： Masahiro Yoshihara , Naofumi Abiko , Katsumi Abe
发明人： Masahiro Yoshihara , Naofumi Abiko , Katsumi Abe
IPC分类号： G11C7/10
CPC分类号： G11C7/1006 , G11C7/106 , G11C7/1087 , G11C16/0483 , G11C16/26
摘要： A sense amplifier circuit is connected to a bit-line and senses and amplifies a signal read from a memory cell. A first data latch is connected to a sense amplifier via a first bus. A second data latch is connected to a second bus. A plurality of circuit groups are repeatedly provided in a first direction, each circuit group including one sense amplifier circuit and one first data latch. The second data latch is provided between the circuit groups and an input/output buffer.
摘要翻译：感测放大器电路连接到位线，并感测并放大从存储器单元读取的信号。第一数据锁存器通过第一总线连接到读出放大器。第二数据锁存器连接到第二总线。多个电路组在第一方向上重复设置，每个电路组包括一个读出放大器电路和一个第一数据锁存器。第二数据锁存器设置在电路组和输入/输出缓冲器之间。

5. 发明授权

US08274845B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08274845B2
公开(公告)日：2012-09-25
申请号：US12793062
申请日：2010-06-03
申请人： Katsumi Abe , Masahiro Yoshihara , Masaru Koyanagi
发明人： Katsumi Abe , Masahiro Yoshihara , Masaru Koyanagi
IPC分类号： G11C7/00 , G11C16/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C16/04 , G11C16/20 , G11C29/02 , G11C29/028 , G11C2207/2254
摘要： A nonvolatile semiconductor memory device is provided, which includes an input buffer provided with a first inverter that can electrically adjust circuit threshold values, a circuit: threshold value monitor provided with a second inverter having the same circuit configuration as the first inverter to detect the circuit threshold values of the first inverter when the input and output of the second inverter are short-circuited, respectively, a memory storing parameter values that correspond to the circuit threshold values detected by the circuit threshold value monitor, and a data-reader circuit reading the parameter values given to the first inverter from the memory.
摘要翻译：提供了一种非易失性半导体存储器件，其包括：输入缓冲器，其具有能够电调节电路阈值的第一反相器;电路：具有与第一反相器相同电路结构的第二反相器的阈值监视器，用于检测电路分别在第二反相器的输入和输出短路时第一反相器的阈值，存储与由电路阈值监视器检测的电路阈值对应的参数值的存储器，读取数据读取器电路的数据读取器电路从存储器给予第一反相器的参数值。

6. 发明授权

US08228744B2 Semiconductor memory device having sense amplifier 有权
标题翻译：具有读出放大器的半导体存储器件
公开(公告)号：US08228744B2
公开(公告)日：2012-07-24
申请号：US12693798
申请日：2010-01-26
申请人： Masahiro Yoshihara , Katsumi Abe
发明人： Masahiro Yoshihara , Katsumi Abe
IPC分类号： G11C7/10
CPC分类号： G11C7/12 , G11C7/08 , G11C2207/005
摘要： A semiconductor memory device includes a memory cell array, a page buffer, a data line pair, a differential amplifier and a precharger. The memory cell array includes a plurality of pages in which a plurality of memory cells are arranged. The page buffer is formed adjacent to the memory cell array, and includes a plurality of sense amplifiers configured to temporarily hold page data read from the memory cells in the page. The data line pair is arranged in the page buffer and is connected to the sense amplifiers. The differential amplifier is configured to amplify a potential difference between lines of the data line pair. The precharger is configured to precharge the data line pair to a predetermined potential. At least one of the differential amplifier and the precharger is formed in the page buffer, and the at least one circuit is electrically connected to the data line pair.
摘要翻译：半导体存储器件包括存储单元阵列，页缓冲器，数据线对，差分放大器和预充电器。存储单元阵列包括多个存储单元布置在其中的多个页面。页面缓冲器形成在与存储单元阵列相邻的位置，并且包括多个读出放大器，被配置为临时保持从页面中的存储器单元读取的页面数据。数据线对被布置在页缓冲器中并连接到读出放大器。差分放大器被配置为放大数据线对的线之间的电位差。预充电器被配置为将数据线对预充电到预定电位。差分放大器和预充电器中的至少一个形成在页面缓冲器中，并且至少一个电路电连接到数据线对。

7. 发明申请

US20110205806A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110205806A1
公开(公告)日：2011-08-25
申请号：US12884721
申请日：2010-09-17
申请人： Masahiro Yoshihara , Teruo Takagiwa , Katsumi Abe
发明人： Masahiro Yoshihara , Teruo Takagiwa , Katsumi Abe
IPC分类号： G11C16/34
CPC分类号： G11C16/3436
摘要： According to one embodiment, a semiconductor memory device includes memory cells, holding circuits, and a logical gate chain. The memory cells are associated with columns. The holding circuits are associated with the columns and capable of holding first information indicating whether associated one of the columns is a verify-failed column or not. The logical gate chain includes a plurality of first logical gates associated with the columns and connected in series. Each of the first logical gates outputs a logical level to a next-stage first logical gate in a series connection. The logical level indicates whether the verify-failed column exists or not based on the first information in associated one of the holding circuit. The content indicated by the logical level output from each of the first logical gates is inverted using one of the first logical gates associated with the verify-failed column as a border.
摘要翻译：根据一个实施例，半导体存储器件包括存储单元，保持电路和逻辑门极链。存储单元与列相关联。保持电路与列相关联，并且能够保存指示相关联的一个列是否为验证失败列的第一信息。逻辑门链包括与列相关联并且串联连接的多个第一逻辑门。第一逻辑门中的每一个在串联连接中将逻辑电平输出到下一级第一逻辑门。逻辑电平基于保持电路中相关联的一个中的第一信息指示验证失败列是否存在。使用与验证失败列相关联的第一逻辑门之一作为边界来反转从每个第一逻辑门输出的逻辑电平指示的内容。

8. 发明申请

US20080291743A1 SEMICONDUCTOR STORAGE DEVICE 失效
标题翻译：半导体存储设备
公开(公告)号：US20080291743A1
公开(公告)日：2008-11-27
申请号：US12123791
申请日：2008-05-20
申请人： Toshiaki Edahiro , Masahiro Yoshihara
发明人： Toshiaki Edahiro , Masahiro Yoshihara
IPC分类号： G11C16/24 , G11C16/26
CPC分类号： G11C16/32 , G11C16/26
摘要： This disclosure concerns a semiconductor storage device including a bit line; a first capacitor supplying a charge to a cell; a first sense node transmitting a potential corresponding to data of the cell; a first pre-charge part charging the bit line, the first capacitor, and the first sense node; a first latch part latching the data; a first sense part including a first sense transistor connected between a power supply and the first latch part, the gate is connected to the first sense node; and a first clamp part connecting a first node between the first latch part and the first sense transistor to the bit line, wherein the first capacitor supplies the charge to the bit line during detecting, and the first sense part supplies a charge from the power supply to the bit line via the first clamp part in response a potential at the first sense node.
摘要翻译：本公开涉及包括位线的半导体存储装置; 向电池提供电荷的第一电容器; 第一感测节点发送对应于所述小区的数据的电位; 对位线充电的第一预充电部分，第一电容器和第一感测节点; 锁定数据的第一锁存部分; 第一感测部分，包括连接在电源和第一锁存部分之间的第一感测晶体管，栅极连接到第一感测节点; 以及将第一锁存部分和第一检测晶体管之间的第一节点连接到位线的第一钳位部分，其中第一电容器在检测期间将电荷提供给位线，并且第一感测部分从电源提供电荷响应于第一感测节点处的电位，经由第一钳位部分到位线。

9. 发明授权

US08902662B2 Memory system having nonvolatile semiconductor memories with control operation having high-current and low-current periods 有权
标题翻译：具有具有高电流和低电流周期的控制操作的非易失性半导体存储器的存储系统
公开(公告)号：US08902662B2
公开(公告)日：2014-12-02
申请号：US13226180
申请日：2011-09-06
申请人： Hitoshi Shiga , Masahiro Yoshihara
发明人： Hitoshi Shiga , Masahiro Yoshihara
IPC分类号： G11C11/34 , G11C16/04 , G11C16/30 , G11C16/10
CPC分类号： G11C16/10 , G11C16/30
摘要： According to one embodiment, a memory system includes a first nonvolatile semiconductor memory, a second nonvolatile semiconductor memory and a controller. The first memory has memory cells and executes a first operation that is at least one of write, read, and erase operations with respect to the memory cells. The first operation includes a first sub-operation and a second-sub operation that consume a current which is equal to or higher than a predetermined current. The second memory has memory cells and executes a second operation that is at least one of write, read, and erase operations with respect to the memory cells. The second operation includes a third sub-operation and a fourth sub-operation that consume a current which is equal to or higher than the predetermined current. The controller controls the first operation and the second operation of the first memory and the second memory.
摘要翻译：根据一个实施例，存储器系统包括第一非易失性半导体存储器，第二非易失性半导体存储器和控制器。第一存储器具有存储器单元并且执行与存储器单元相关的写入，读取和擦除操作中的至少一个的第一操作。第一操作包括消耗等于或高于预定电流的电流的第一子操作和第二子操作。第二存储器具有存储单元并且执行与存储单元相关的写入，读取和擦除操作中的至少一个的第二操作。第二操作包括消耗等于或高于预定电流的电流的第三子操作和第四子操作。控制器控制第一存储器和第二存储器的第一操作和第二操作。

10. 发明申请

US20120250409A1 SEMICONDUCTOR MEMORY AND CONTROL METHOD THEREOF 有权
标题翻译：半导体存储器及其控制方法
公开(公告)号：US20120250409A1
公开(公告)日：2012-10-04
申请号：US13235430
申请日：2011-09-18
申请人： Hiroyuki KAGA , Masahiro Yoshihara , Naofumi Abiko
发明人： Hiroyuki KAGA , Masahiro Yoshihara , Naofumi Abiko
IPC分类号： G11C16/04
CPC分类号： G11C11/4096 , G11C11/5642 , G11C16/0483 , G11C16/08
摘要： According to one embodiment, a semiconductor memory includes a memory cell array which includes memory cells, the memory cells being arranged along a row direction and a column direction and storing data respectively corresponding to thresholds, a row control circuit which controls a row of the memory cell array, and a column control circuit which includes a control unit, the control unit generating a signal to control elements corresponding to column of the memory cell array in accordance with a pointer corresponding to an external address signal.
摘要翻译：根据一个实施例，半导体存储器包括存储单元阵列，存储单元阵列包括存储单元，存储单元沿着行方向和列方向排列，并且分别存储对应于阈值的数据，控制存储器行的行控制电路单元阵列和列控制电路，其包括控制单元，所述控制单元根据与外部地址信号对应的指针，产生对应于存储单元阵列的列的控制元件的信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式