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1. 发明授权

US07379442B2 Method and apparatus for buffer storage of data packets which are to be transmitted via a connection that has been set up 有权
标题翻译：用于缓冲存储要通过已经建立的连接发送的数据分组的方法和装置
公开(公告)号：US07379442B2
公开(公告)日：2008-05-27
申请号：US10491347
申请日：2002-09-19
申请人： Malte Borsum , Klaus Gaedke , Thomas Brune
发明人： Malte Borsum , Klaus Gaedke , Thomas Brune
IPC分类号： H04Q7/24 , H04L12/28 , H04L12/54
CPC分类号： G06F5/10 , G06F5/065 , H04L47/621 , H04L49/90 , H04L49/9031 , H04L49/9036
摘要： So-called LCH packets are defined in the Hiperlan Type 2 System for wire-free transmission of video and audio data streams. These LCH packets have a length of 54 data bytes. Furthermore, the Hiperlan/2 Standard provides for so-called ARQ messages to be sent back to the transmitter in an SCH packet in a QOS mode (Quality Of Service), in which all the LCH data packets must be confirmed by the receiver. Space for the LCH and SCH data packets must be provided in a buffer store in the Hiperlan/2 interface for each connection that is set up. When there is a possibility of several hundred connections having been set up, separate reservation of memory areas for LCH and SCH packets would involve considerable complexity for the memory organization. The invention proposes that only one common area be reserved for LCH and SCH packets in the buffer store. The section which is provided for each LCH package is of such a size that it corresponds to a value 2n where nε[0, 1, 2, 3, . . . ], and this results in the hardware unit for the address calculation of these data section starts being greatly simplified. However, the area is chosen to be larger than actually required for the buffer storage of one LCH packet. The SCH packets, which likewise need to be buffer-stored, are entered in the unused part of such a section for an LCH packet. This considerably reduces the complexity for memory organization without having to leave a major proportion of the memory unused.
摘要翻译：在Hiperlan Type 2系统中定义了所谓的LCH分组，用于视频和音频数据流的无线传输。这些LCH数据包的长度为54个数据字节。此外，Hiperlan / 2标准提供所谓的ARQ消息，以QOS模式（服务质量）发送回发送方，其中所有LCH数据分组必须由接收机确认。必须在设置的每个连接的Hiperlan / 2接口的缓冲存储器中提供LCH和SCH数据包的空间。当存在已经建立了数百个连接的可能性时，用于LCH和SCH分组的存储区域的单独预留将涉及存储器组织的相当大的复杂性。本发明提出在缓冲存储器中仅为LCH和SCH分组保留一个公共区域。为每个LCH封装提供的部分具有这样的尺寸，使得其对应于值n 2，其中nepsilon [0,1,2,3，...，。。 ]，这导致这些数据部分的地址计算的硬件单元开始被大大简化。然而，该区域被选择为大于实际需要的一个LCH分组的缓冲存储器。同样需要缓冲存储的SCH分组被输入到用于LCH分组的这种部分的未使用部分中。这大大降低了内存组织的复杂性，而无需留下大部分内存未使用。

2. 发明授权

US06810045B1 Method and device for processing data packets which have been received or are to be transmitted on a data channel 有权
标题翻译：用于处理已经在数据信道上接收或要发送的数据分组的方法和装置
公开(公告)号：US06810045B1
公开(公告)日：2004-10-26
申请号：US09623053
申请日：2000-08-24
申请人： Thomas Brune , Klaus Gaedke , Siegfried Schweidler
发明人： Thomas Brune , Klaus Gaedke , Siegfried Schweidler
IPC分类号： H04J300
CPC分类号： H04L12/40058 , G06F13/387 , H04L12/40117
摘要： The invention relates to a way of implementing the so-called “late” check according to IEC 61883 in a link layer IC for the IEEE 1394 Serial Bus in a way which is favourable in terms of expenditure. According to the invention, a specific time model is used which, during the checking of the up-to-dateness of a data packet by comparison with the current bus time, also substantially simplifies the necessary comparison operations by virtue of the fact that it is possible to represent only sections of the time axis by means of a data word with limited bit length.
摘要翻译：本发明涉及在IEEE 1394串行总线的链路层IC中以一种有利于支出的方式实现根据IEC 61883所谓的“后期”检查的方式。根据本发明，使用特定的时间模型，在通过与当前总线时间比较来检查数据分组的最新状态期间，基本上简化了必要的比较操作，因为它是可能仅通过具有有限位长度的数据字来表示时间轴的部分。

3. 发明授权

US08352780B2 Method and apparatus for dealing with write errors when writing information data into flash memory devices 有权
标题翻译：在将信息数据写入闪存设备时处理写入错误的方法和装置
公开(公告)号：US08352780B2
公开(公告)日：2013-01-08
申请号：US12819432
申请日：2010-06-21
申请人： Thomas Brune , Michael Drexler , Dieter Haupt
发明人： Thomas Brune , Michael Drexler , Dieter Haupt
IPC分类号： G06F11/00
CPC分类号： G06F11/141 , G06F12/0246 , G06F2212/7209 , G11C29/70
摘要： For writing, flash memory devices are physically accessed in a page-oriented mode, but such devices are not error-free in operation. According to the invention, when writing information data in a bus write cycle in a sequential manner into flash memory devices assigned to a common data bus, at least one of said flash memory devices is not fed for storage with a current section of said information data. In case an error is occurring while writing a current information data section into a page of a current one of said flash memory devices, said current information data section is written into a non-flash memory. During the following bus write cycle, while the flash memory device containing that defective page is normally idle, that idle time period is used for copying the corresponding stored section of said information data from said non-flash memory to a non-defect page of that flash memory device.
摘要翻译：对于写入，闪存设备以面向页面的模式进行物理访问，但是这样的设备在操作中不会出错。根据本发明，当将总线写入周期中的信息数据以顺序的方式写入分配给公共数据总线的闪存器件中时，所述闪存器件中的至少一个不被馈送用于与所述信息数据的当前部分一起存储。如果在将当前信息数据部分写入当前所述闪速存储器件的页面中发生错误的情况下，将所述当前信息数据部分写入非闪存存储器。在下一个总线写周期期间，当包含该故障页的闪存设备通常是空闲时，该空闲时间段用于将所述信息数据的相应存储部分从所述非闪存存储器复制到该非闪存存储器的非缺陷页闪存设备。

4. 发明授权

US08028096B2 Method for using the hand-held device in a multimedia home network 有权
标题翻译：在多媒体家庭网络中使用手持设备的方法
公开(公告)号：US08028096B2
公开(公告)日：2011-09-27
申请号：US10363907
申请日：2001-09-03
申请人： Thomas Brune , Dirk Adolph , Axel Kochale , Andrei Chevtsov
发明人： Thomas Brune , Dirk Adolph , Axel Kochale , Andrei Chevtsov
IPC分类号： G06F15/16 , G06F9/44 , G06F9/445
CPC分类号： H04M1/72561 , H04M1/72522 , H04M1/72527 , H04M1/7253 , H04W4/00 , H04W76/10 , H04W88/02
摘要： The present invention relates to a hand-held device comprising connection means for supporting an internet data transmission link between the hand-held device and the internet; browser means for fetching internet data from the internet; input means for receiving a user input; and generating means for generating a command script in response to said user input, where said command script is related to said searched internet data; where said command script, when the hand-held device is connected to a multimedia home device, can be processed to initiate a transmission of at least part of said searched internet data and/or other internet data to said multimedia home device.
摘要翻译：手持式装置技术领域本发明涉及一种手持式装置，包括用于支持手持设备和因特网之间的因特网数据传输链路的连接装置; 用于从互联网获取互联网数据的浏览器; 用于接收用户输入的输入装置; 以及产生装置，用于响应于所述用户输入生成命令脚本，其中所述命令脚本与所述搜索的互联网数据相关; 其中所述命令脚本在手持设备连接到多媒体家庭设备时可被处理以发起至少部分所述搜索的互联网数据和/或其他因特网数据到所述多媒体家庭设备的传输。

5. 发明申请

US20100005205A1 Device For Processing A Stream Of Data Words 有权
标题翻译：用于处理数据字串的设备
公开(公告)号：US20100005205A1
公开(公告)日：2010-01-07
申请号：US12310749
申请日：2007-09-04
申请人： Thomas Brune , Michael Walden , Oliver Kamphenket , Herbert Schuetze
发明人： Thomas Brune , Michael Walden , Oliver Kamphenket , Herbert Schuetze
IPC分类号： G06F13/42 , H04L29/02
CPC分类号： G06F13/4031
摘要： State of the art processor systems, esp. in embedded systems, are not able to process data under real-time conditions especially with throughput rates near 10 Gbps. So, when using interfaces like PCI Express (PCIe) or Infiniband or 10G-Ethernet for 10 Gbps data throughput, special data-paths have to process the high throughput rate data. But tasks like connection management or time uncritical control messaging are better manageable by a processor. According to the invention it is proposed a kind of multiplexer architecture that is needed to split between control and data-path access for a PCI Express based architecture.
摘要翻译：最先进的处理器系统，尤其是在嵌入式系统中，无法在实时条件下处理数据，特别是在接近10 Gbps的吞吐率下。因此，当使用PCI Express（PCIe）或Infiniband或10G以太网等接口进行10 Gbps数据吞吐量时，特殊数据路径必须处理高吞吐率数据。但是，诸如连接管理或时间不关键控制消息传递的任务更好地被处理器管理。根据本发明，提出了一种在基于PCI Express的架构的控制和数据路径访问之间分割所需的多路复用器架构。

6. 发明申请

US20050050259A1 Method for multibank memory scheduling 失效
标题翻译：多段内存调度方法
公开(公告)号：US20050050259A1
公开(公告)日：2005-03-03
申请号：US10915067
申请日：2004-08-10
申请人： Tim Niggemeier , Thomas Brune
发明人： Tim Niggemeier , Thomas Brune
IPC分类号： G06F12/06 , G06F12/02 , G11C7/10 , G11C11/407 , G06F12/00
CPC分类号： G11C7/1042
摘要： The present invention relates to a method for scheduling and controlling access to a multibank memory having at least two banks, and to an apparatus for reading from and/or writing to recording media using such method. According to the invention, the method comprises the steps of: writing an input stream to the first bank; switching the writing of the input stream to the second bank when a read command for the first bank is received; and switching the writing of the input stream back to the first bank when a read command for the second bank is received.
摘要翻译：本发明涉及一种用于调度和控制对具有至少两个存储体的多存储器存取的方法，以及一种用于使用这种方法从记录介质读取和/或写入记录介质的装置。根据本发明，该方法包括以下步骤：将输入流写入第一存储体; 当接收到用于第一组的读取命令时，将输入流的写入切换到第二存储体; 以及当接收到用于所述第二存储体的读取命令时，将所述输入流的写入切换回所述第一存储体。

7. 发明申请

US20130138875A1 STORING/READING SEVERAL DATA STREAMS INTO/FROM AN ARRAY OF MEMORIES 有权
标题翻译：存储/读取存储/存储阵列中的几个数据流
公开(公告)号：US20130138875A1
公开(公告)日：2013-05-30
申请号：US13816250
申请日：2011-08-08
申请人： Oliver Kamphenkel , Thomas Brune , Michael Drexler , Stefan Abeling
发明人： Oliver Kamphenkel , Thomas Brune , Michael Drexler , Stefan Abeling
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F13/1684 , G06F2212/7202 , G06F2212/7203 , G06F2212/7208
摘要： High speed mass storage devices using NAND flash memories (MDY.X) are suitable for recording and playing back a video data stream under real-time conditions, wherein the data are handled page-wise in the flash memories and are written in parallel to multiple memory buses (MBy). However, for operating with multiple independent data streams a significant buffer size is required. According to the invention, data from different data streams are collected in corresponding different buffers (FIFO 1, . . . , FIFO Z) until the amount of collected data in a current buffer corresponds to a current one of the data blocks. Then, the data of the current data block from the current buffer are stored into memories connected to a current one of the memory buses, wherein the following buffered data block of the related data stream is later on stored into memories connected to a following one of the memory buses, the number of the following memory bus being increased with respect to the number of the current memory bus. These steps are repeated, also for the other ones of the data streams using other available ones of the buffers and other ones of the memory buses. In combination with a corresponding buffer control it is possible to allocate and use a minimum number of buffers in a flexible way.
摘要翻译：使用NAND闪速存储器（MDY.X）的高速大容量存储装置适用于在实时条件下记录和重放视频数据流，其中数据在闪速存储器中被逐页地处理并被并行写入多个内存总线（MBy）。然而，对于使用多个独立数据流进行操作，需要显着的缓冲区大小。根据本发明，来自不同数据流的数据被收集在相应的不同缓冲器（FIFO 1，...，FIFO Z）中，直到当前缓冲器中收集的数据量对应于当前数据块中的一个。然后，将来自当前缓冲器的当前数据块的数据存储到连接到当前一个存储器总线的存储器中，其中相关数据流的后续缓冲数据块稍后被存储到连接到下一个存储器总线存储器总线，相对于当前存储器总线的数量增加了以下存储器总线的数量。重复这些步骤，对于使用缓冲器中的其他可用缓冲器和其它存储器总线的数据流中的其他步骤也是如此。结合相应的缓冲区控制，可以以灵活的方式分配和使用最少数量的缓冲区。

8. 发明授权

US08285932B2 Mass storage system with improved usage of buffer capacity 有权
标题翻译：大容量存储系统具有更好的缓冲容量使用能力
公开(公告)号：US08285932B2
公开(公告)日：2012-10-09
申请号：US12733338
申请日：2008-08-26
申请人： Stefan Abeling , Johann Maas , Wolfgang Klausberger , Thomas Brune
发明人： Stefan Abeling , Johann Maas , Wolfgang Klausberger , Thomas Brune
IPC分类号： G06F12/00
CPC分类号： G06F3/0658 , G06F3/0608 , G06F3/0656 , G06F3/0689
摘要： The present invention relates to a mass storage system with improved usage of buffer capacity, and more specifically to a mass storage system for real-time data storage with an embedded controller. According to the invention, the mass storage system has a first data path between a real-time data interface and a mass storage array, the first data path including a data buffer without access latency, and a second data path between an embedded processor and the mass storage array, wherein the data buffer without access latency is also used as a data buffer for non real-time data transfers between the embedded processor and the mass storage array.
摘要翻译：本发明涉及具有改进的缓冲器容量使用的大容量存储系统，更具体地涉及一种用于利用嵌入式控制器实时数据存储的海量存储系统。根据本发明，大容量存储系统具有实时数据接口和大容量存储阵列之间的第一数据路径，第一数据路径包括无访问延迟的数据缓冲器，以及嵌入式处理器与第二数据路径之间的第二数据路径大容量存储阵列，其中没有访问延迟的数据缓冲器也用作用于嵌入式处理器和大容量存储阵列之间的非实时数据传输的数据缓冲器。

9. 发明授权

US08234448B2 Redundancy protected mass storage system with increased performance 有权
标题翻译：冗余保护大容量存储系统，性能更高
公开(公告)号：US08234448B2
公开(公告)日：2012-07-31
申请号：US12733292
申请日：2008-08-05
申请人： Stefan Abeling , Wolfgang Klausberger , Thomas Brune , Axel Kochale
发明人： Stefan Abeling , Wolfgang Klausberger , Thomas Brune , Axel Kochale
IPC分类号： G06F12/16
CPC分类号： G06F11/1088 , G06F11/1076 , G06F2211/1016 , H04N21/2182 , H04N21/2318
摘要： The present invention relates to a redundancy protected mass storage system with increased performance, and more specifically to a mass storage system with multiple storage units. According to the invention, the resources that are essentially provided for compensating the damage of one or more storage units are also used to enhance the system performance. For this purpose during reading or writing the storage system just waits for the responses of a minimum number of required storage units to start reading or writing, respectively.
摘要翻译：本发明涉及具有增强性能的冗余保护大容量存储系统，更具体地说涉及具有多个存储单元的大容量存储系统。根据本发明，基本上提供用于补偿一个或多个存储单元的损坏的资源也用于增强系统性能。为此，在读取或写入存储系统时，只需等待最少数量的所需存储单元的响应即可开始读取或写入。

10. 发明授权

US06618832B1 Method and bus interface employing a memory in an intergrated circuit which is used to link a bus with an application device to be controlled by the bus 有权
标题翻译：方法和总线接口，采用集成电路中的存储器，该存储器用于将总线与应用设备链接以由总线控制
公开(公告)号：US06618832B1
公开(公告)日：2003-09-09
申请号：US09515660
申请日：2000-02-29
申请人： Siegfried Schweidler , Thomas Brune
发明人： Siegfried Schweidler , Thomas Brune
IPC分类号： H03M1305
CPC分类号： H04L49/9057 , H04L1/0061 , H04L1/0072 , H04L12/40058 , H04L12/40071 , H04L49/90 , H04L49/901 , H04L49/9036 , H04L49/9084 , H04L49/9089
摘要： The IEEE1394 bus communication protocol has three layers: physical layer, link layer, and transaction layer. A link layer IC implements the interface to an external application and prepares data for sending on the bus, or interprets incoming data packets from the IEEE1394 bus. A physical layer IC implements the direct electrical connection to the bus and controls many functions including arbitration for sending data on the bus. According to the invention the capacity of the on-chip memory becomes assigned in a flexible way in order to be able to meet the requirements for any specific service. Further, the on-chip memory is prevented from storing data packets containing transmission errors by CRC checking on the fly header data and other data. This is performed for asynchronous data packets as well as isochronous data packets, and allows to have a minimum on-chip memory capacity only.
摘要翻译： IEEE1394总线通信协议有三层：物理层，链路层和事务层。链路层IC实现与外部应用的接口，并准备用于在总线上发送的数据，或解释来自IEEE1394总线的传入数据分组。物理层IC实现与总线的直接电连接，并控制许多功能，包括在总线上发送数据的仲裁。根据本发明，以灵活的方式分配片上存储器的容量，以便能够满足任何特定服务的要求。此外，片上存储器被防止通过对毛头数据和其他数据的CRC校验来存储包含传输错误的数据分组。这是针对异步数据包和同步数据包执行的，并且允许仅具有最小的片上存储容量。

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