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1. 发明申请

US20110256672A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20110256672A1
公开(公告)日：2011-10-20
申请号：US13172330
申请日：2011-06-29
申请人： Makoto WADA , Kazuyuki HIGASHI , Naofumi NAKAMURA , Tsuneo UENAKA
发明人： Makoto WADA , Kazuyuki HIGASHI , Naofumi NAKAMURA , Tsuneo UENAKA
IPC分类号： H01L21/8239
CPC分类号： H01L23/481 , H01L21/76808 , H01L21/76816 , H01L23/5226 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof.
摘要翻译：非易失性半导体存储器件包括存储器串和布线。存储器串包括半导体层，电荷存储层和多个第一导电层。多个第一导电层包括形成为阶梯形状的阶梯部分，使得多个第一导电层的端部的位置彼此不同。布线包括从包括台阶部分的第一导电层的上表面向上延伸的多个第二导电层。多个第二导电层形成为使得其上端与平行于基板的表面对齐，并且其直径从其上端向下端减小。多个第二导电层形成为使得其在垂直方向上的长度越大，其上端的直径越大。

2. 发明申请

US20100213526A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20100213526A1
公开(公告)日：2010-08-26
申请号：US12615598
申请日：2009-11-10
申请人： Makoto WADA , Kazuyuki HIGASHI , Naofumi NAKAMURA , Tsuneo UENAKA
发明人： Makoto WADA , Kazuyuki HIGASHI , Naofumi NAKAMURA , Tsuneo UENAKA
IPC分类号： H01L29/792 , H01L21/8239
CPC分类号： H01L23/481 , H01L21/76808 , H01L21/76816 , H01L23/5226 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof.
摘要翻译：非易失性半导体存储器件包括存储器串和布线。存储器串包括半导体层，电荷存储层和多个第一导电层。多个第一导电层包括形成为阶梯形状的阶梯部分，使得多个第一导电层的端部的位置彼此不同。布线包括从包括台阶部分的第一导电层的上表面向上延伸的多个第二导电层。多个第二导电层形成为使得其上端与平行于基板的表面对齐，并且其直径从其上端向下端减小。多个第二导电层形成为使得其在垂直方向上的长度越大，其上端的直径越大。

3. 发明申请

US20100207186A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20100207186A1
公开(公告)日：2010-08-19
申请号：US12706195
申请日：2010-02-16
申请人： Kazuyuki HIGASHI , Tsuneo Uenaka
发明人： Kazuyuki HIGASHI , Tsuneo Uenaka
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11578 , H01L27/11575 , H01L27/11582
摘要： A first region comprises: a semiconductor layer including a columnar portion, a charge storage layer, and a plurality of first conductive layers. The second region comprises: a plurality of second conductive layers formed in the same layer as the plurality of first conductive layers. The plurality of first conductive layers configure a stepped portion at an end vicinity of the first region. The stepped portion is formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The plurality of second conductive layers is formed such that positions of ends thereof at an end vicinity of the second region surrounding the first region are aligned in substantially the perpendicular direction to the substrate.
摘要翻译：第一区域包括：包括柱状部分，电荷存储层和多个第一导电层的半导体层。第二区域包括：与多个第一导电层形成在同一层中的多个第二导电层。多个第一导电层在第一区域的附近的端部处构成阶梯部。阶梯部形成为阶梯状，使得多个第一导电层的端部的位置彼此不同。多个第二导电层形成为使得围绕第一区域的第二区域的端部附近的端部的位置基本上与基板垂直的方向排列。

4. 发明申请

US20090289281A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：用于制造半导体器件的半导体器件和方法
公开(公告)号：US20090289281A1
公开(公告)日：2009-11-26
申请号：US12468504
申请日：2009-05-19
申请人： Makoto WADA , Akihiro KAJITA , Kazuyuki HIGASHI
发明人： Makoto WADA , Akihiro KAJITA , Kazuyuki HIGASHI
IPC分类号： H01L29/66
CPC分类号： H01L23/522 , H01L21/76816 , H01L21/76849 , H01L21/76852 , H01L21/76885 , H01L21/76895 , H01L23/5226 , H01L27/10885 , H01L27/10888 , H01L27/11517 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a plurality of bit lines repeatedly arranged with a same line width and pitch in a memory device region; a plurality of shunt lines arranged in a same layer as that of the plurality of bit lines, in parallel therewith, and with the same line width and pitch as those of the plurality of bit lines in the memory device region; and an upper-layer contact plug arranged from an upper-layer side so as to be connected to the plurality of shunt lines by extending over two or more shunt lines.
摘要翻译：半导体器件包括在存储器件区域中以相同的线宽和间距重复排列的多个位线; 与多个位线的平行布置在与该多个位线相同层的多个分流线，并且与存储器件区域中的多个位线的线宽和间距相同; 以及从上层侧配置的上层接触插塞，以便通过在两条或多条分路线上延伸而连接到多条分路线。

5. 发明申请

US20090191712A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：US20090191712A1
公开(公告)日：2009-07-30
申请号：US12208010
申请日：2008-09-10
申请人： Kazuyuki HIGASHI , Takuji Kuniya , Makoto Wada , Akihiro Kajita
发明人： Kazuyuki HIGASHI , Takuji Kuniya , Makoto Wada , Akihiro Kajita
IPC分类号： H01L21/308
CPC分类号： H01L21/0273 , H01L21/0337 , H01L21/0338
摘要： In one aspect of the present invention, a method of manufacturing a semiconductor device may include forming a first film on an amorphous silicon layer to be patterned, the first film and the amorphous film having a line-and-space ratio of approximately 3:1, sliming down, after processing the first film, a line portion of the pattern from both longitudinal sides of the line portion until the width of the line portion is reduced to approximately one third, reforming a part of the amorphous silicon layer where the first film is not provided such that reformed part has different etching ratio, and removing the first film and the amorphous silicon layer other than reformed part.
摘要翻译：在本发明的一个方面中，制造半导体器件的方法可以包括在待图案化的非晶硅层上形成第一膜，第一膜和非线性膜的线间距比约为3:1 ，在对第一膜进行处理之后，将该图案的线部分从线部分的两个纵向侧线直到线部分的宽度减小到大约三分之一，在下一步处理之后，将非晶硅层的一部分重新形成第一膜不能使重整部分具有不同的蚀刻比，并除去除了重整部分以外的第一膜和非晶硅层。

6. 发明申请

US20110057251A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20110057251A1
公开(公告)日：2011-03-10
申请号：US12875766
申请日：2010-09-03
申请人： Kazuyuki HIGASHI
发明人： Kazuyuki HIGASHI
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L27/11578 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L29/78642
摘要： A nonvolatile semiconductor memory device includes a first region having a plurality of electrically rewritable memory cells disposed therein, and a second region adjacent to the first region. The nonvolatile semiconductor memory device includes a plurality of first conductive layers, a semiconductor layer, a charge storage layer, and an insulating columnar layer. The plurality of first conductive layers are stacked in the first region and the second region, and include a stepped portion in the second region, positions of ends of the plurality of first conductive layers being different in the stepped portion. The semiconductor layer is surrounded by the first conductive layers in the first region, includes a first columnar portion extending in a stacking direction. The charge storage layer is formed between the first conductive layers and a side surface of the first columnar portion. The insulating columnar layer is surrounded by the first conductive layers in the stepped portion, and includes a second columnar portion extending in the stacking direction and comprising an insulator.
摘要翻译：非易失性半导体存储器件包括具有设置在其中的多个电可重写存储单元的第一区域和与第一区域相邻的第二区域。非易失性半导体存储器件包括多个第一导电层，半导体层，电荷存储层和绝缘柱状层。多个第一导电层层叠在第一区域和第二区域中，并且在第二区域中包括阶梯部分，多个第一导电层的端部的位置在阶梯部分中不同。半导体层被第一区域中的第一导电层围绕，包括沿堆叠方向延伸的第一柱状部分。电荷存储层形成在第一导电层与第一柱状部分的侧面之间。绝缘柱状层被台阶部分的第一导电层包围，并且包括在层叠方向上延伸并包括绝缘体的第二柱状部分。

7. 发明申请

US20120068252A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20120068252A1
公开(公告)日：2012-03-22
申请号：US13043714
申请日：2011-03-09
申请人： Ryota KATSUMATA , Kazuyuki HIGASHI , Yoshiaki FUKUZUMI
发明人： Ryota KATSUMATA , Kazuyuki HIGASHI , Yoshiaki FUKUZUMI
IPC分类号： H01L29/792
CPC分类号： H01L27/11582 , H01L27/11575 , H01L29/7926
摘要： According to one embodiment, a semiconductor memory device includes a substrate, a multilayer body, a semiconductor member and a charge storage layer. The multilayer body is provided on the substrate, with a plurality of insulating films and electrode films alternately stacked, and includes a first staircase and a second staircase opposed to each other. The semiconductor member is provided in the multilayer body outside a region provided with the first staircase and the second staircase, and the semiconductor member extends in stacking direction of the insulating films and the electrode films. The charge storage layer is provided between each of the electrode films and the semiconductor member. The each of the electrode films includes a first terrace formed in the first staircase, a second terrace formed in the second staircase and a bridge portion connecting the first terrace and the second terrace.
摘要翻译：根据一个实施例，半导体存储器件包括衬底，多层体，半导体构件和电荷存储层。多层体设置在基板上，多个绝缘膜和电极膜交替堆叠，并且包括彼此相对的第一阶梯和第二阶梯。半导体构件设置在设置有第一阶梯和第二阶梯的区域之外的多层体中，并且半导体构件在绝缘膜和电极膜的堆叠方向上延伸。电荷存储层设置在每个电极膜和半导体部件之间。每个电极膜包括形成在第一阶梯中的第一台阶，形成在第二楼梯中的第二台阶和连接第一台阶和第二平台的桥接部分。

8. 发明申请

US20130234339A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME, AND MANAGEMENT SYSTEM OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及其制造方法以及半导体器件的管理系统
公开(公告)号：US20130234339A1
公开(公告)日：2013-09-12
申请号：US13601088
申请日：2012-08-31
申请人： Kazuyuki HIGASHI , Yoshiaki Sugizaki
发明人： Kazuyuki HIGASHI , Yoshiaki Sugizaki
IPC分类号： H01L21/82 , H01L23/538
CPC分类号： H01L21/82 , H01L21/6835 , H01L21/6836 , H01L21/76898 , H01L22/14 , H01L22/20 , H01L23/481 , H01L23/5384 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/6834 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/48464 , H01L2224/73257 , H01L2224/83005 , H01L2224/9202 , H01L2224/94 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014 , H01L2924/10253 , H01L2924/1434 , H01L2924/15311 , H01L2924/37001 , H01L2924/00 , H01L2224/83 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： After stacking m wafers in each of which a plurality of semiconductor chips are formed, the m wafers are diced to semiconductor chips to form a first chip stack having m of the semiconductor chips stacked, and, after stacking n wafers, the n wafers are diced to semiconductor chips to form a second chip stack having n of the semiconductor chips stacked. Next, the first chip stack is sorted according to the number of defective semiconductor chips included in the first chip stack, and the second chip stack is sorted according to the number of defective semiconductor chips included in the second chip stack. Furthermore, the first chip stack or the second chip stack after sorting are combined to form a third chip stack.
摘要翻译：在堆叠形成多个半导体芯片的m个晶片之后，将m个晶片切割成半导体芯片，以形成堆叠有半导体芯片m的第一芯片堆叠，并且在堆叠n个晶片之后，将n个晶片切割形成半导体芯片堆叠的n个第二芯片堆叠。接下来，根据包括在第一芯片堆栈中的缺陷半导体芯片的数量对第一芯片堆叠进行分类，并且根据包括在第二芯片堆栈中的缺陷半导体芯片的数量对第二芯片堆栈进行分类。此外，将排序之后的第一芯片堆叠或第二芯片堆叠组合以形成第三芯片堆叠。

9. 发明申请

US20110216597A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110216597A1
公开(公告)日：2011-09-08
申请号：US12882512
申请日：2010-09-15
申请人： Kazuyuki HIGASHI , Tadashi Iguchi
发明人： Kazuyuki HIGASHI , Tadashi Iguchi
IPC分类号： G11C16/04
CPC分类号： H01L27/11582 , G11C16/0483
摘要： A memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The semiconductor layer includes a columnar portion that extends in a perpendicular direction to a substrate. The charge storage layer is formed around a side surface of the columnar portion. The plurality of first conductive layers are formed around the side surface of the columnar portion and the charge storage layer. A control circuit comprises a plurality of second conductive layers, an insulating layer, and a plurality of plug layers. The plurality of second conductive layers are formed in the same layers as the plurality of first conductive layers. The insulating layer is formed penetrating the plurality of second conductive layers in the perpendicular direction. The plurality of plug layers are formed penetrating the insulating layer in the perpendicular direction. The insulating layer has a rectangular shaped cross-section with a constricted portion in a horizontal direction to the substrate. The constricted portion is positioned on a long side of the cross-section.
摘要翻译：存储器串包括半导体层，电荷存储层和多个第一导电层。半导体层包括沿与基板垂直的方向延伸的柱状部分。电荷存储层围绕柱状部分的侧表面形成。多个第一导电层围绕柱状部分和电荷存储层的侧表面形成。控制电路包括多个第二导电层，绝缘层和多个插塞层。多个第二导电层形成在与多个第一导电层相同的层中。绝缘层形成为沿着垂直方向穿过多个第二导电层。多个插塞层在垂直方向上形成为穿透绝缘层。绝缘层具有矩形截面，在基板的水平方向上具有缩颈部分。收缩部分位于横截面的长边上。

10. 发明申请

US20090317978A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：US20090317978A1
公开(公告)日：2009-12-24
申请号：US12487979
申请日：2009-06-19
申请人： Kazuyuki HIGASHI
发明人： Kazuyuki HIGASHI
IPC分类号： H01L21/311
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： In one aspect of the present invention, a method of manufacturing semiconductor device may include forming a second core on a member to be processed, and a first core on the second core, the second core located below the first core and having a width larger than that of the first core, forming a coating film on a top surface and side surfaces of the first core, and a top surface and side surfaces of the second core, processing the coating film into sidewall masks by partially removing the coating film in a manner that portions of the coating film, which are located on the side surfaces of the first and second cores, are left remaining, etching the first and second cores by using the sidewall masks as a mask so as to remove the first core and portions of the second core which are not covered with the sidewall masks from above, so that an etching mask including the sidewall masks and portions of the second core which remain directly below the sidewall masks is formed, and etching the member by using the etching mask as a mask, so that the member is patterned.
摘要翻译：在本发明的一个方面中，制造半导体器件的方法可以包括在要加工的部件上形成第二芯，在第二芯上形成第一芯，第二芯位于第一芯的下方，其宽度大于第一芯的第一芯在第一芯的顶表面和侧表面以及第二芯的顶表面和侧表面上形成涂膜，通过以一定程度的部分去除涂膜将涂膜加工成侧壁掩模位于第一和第二芯的侧表面上的涂膜的部分留下，通过使用侧壁掩模作为掩模蚀刻第一和第二芯，以便去除第一芯和第二芯的部分第二芯，其不被来自上面的侧壁掩模覆盖，从而形成包括侧壁掩模的蚀刻掩模和保持在侧壁掩模正下方的第二芯的部分，并蚀刻该内存通过使用蚀刻掩模作为掩模，使得构件被图案化。

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