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    • 6. 发明申请
    • SEMICONDUCTOR MEMORY DEVICE
    • 半导体存储器件
    • US20120068252A1
    • 2012-03-22
    • US13043714
    • 2011-03-09
    • Ryota KATSUMATAKazuyuki HIGASHIYoshiaki FUKUZUMI
    • Ryota KATSUMATAKazuyuki HIGASHIYoshiaki FUKUZUMI
    • H01L29/792
    • H01L27/11582H01L27/11575H01L29/7926
    • According to one embodiment, a semiconductor memory device includes a substrate, a multilayer body, a semiconductor member and a charge storage layer. The multilayer body is provided on the substrate, with a plurality of insulating films and electrode films alternately stacked, and includes a first staircase and a second staircase opposed to each other. The semiconductor member is provided in the multilayer body outside a region provided with the first staircase and the second staircase, and the semiconductor member extends in stacking direction of the insulating films and the electrode films. The charge storage layer is provided between each of the electrode films and the semiconductor member. The each of the electrode films includes a first terrace formed in the first staircase, a second terrace formed in the second staircase and a bridge portion connecting the first terrace and the second terrace.
    • 根据一个实施例,半导体存储器件包括衬底,多层体,半导体构件和电荷存储层。 多层体设置在基板上,多个绝缘膜和电极膜交替堆叠,并且包括彼此相对的第一阶梯和第二阶梯。 半导体构件设置在设置有第一阶梯和第二阶梯的区域之外的多层体中,并且半导体构件在绝缘膜和电极膜的堆叠方向上延伸。 电荷存储层设置在每个电极膜和半导体部件之间。 每个电极膜包括形成在第一阶梯中的第一台阶,形成在第二楼梯中的第二台阶和连接第一台阶和第二平台的桥接部分。
    • 7. 发明申请
    • NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    • 非易失性半导体存储器件及其制造方法
    • US20110057251A1
    • 2011-03-10
    • US12875766
    • 2010-09-03
    • Kazuyuki HIGASHI
    • Kazuyuki HIGASHI
    • H01L29/792H01L21/28
    • H01L27/11578H01L27/11524H01L27/11551H01L27/11556H01L29/78642
    • A nonvolatile semiconductor memory device includes a first region having a plurality of electrically rewritable memory cells disposed therein, and a second region adjacent to the first region. The nonvolatile semiconductor memory device includes a plurality of first conductive layers, a semiconductor layer, a charge storage layer, and an insulating columnar layer. The plurality of first conductive layers are stacked in the first region and the second region, and include a stepped portion in the second region, positions of ends of the plurality of first conductive layers being different in the stepped portion. The semiconductor layer is surrounded by the first conductive layers in the first region, includes a first columnar portion extending in a stacking direction. The charge storage layer is formed between the first conductive layers and a side surface of the first columnar portion. The insulating columnar layer is surrounded by the first conductive layers in the stepped portion, and includes a second columnar portion extending in the stacking direction and comprising an insulator.
    • 非易失性半导体存储器件包括具有设置在其中的多个电可重写存储单元的第一区域和与第一区域相邻的第二区域。 非易失性半导体存储器件包括多个第一导电层,半导体层,电荷存储层和绝缘柱状层。 多个第一导电层层叠在第一区域和第二区域中,并且在第二区域中包括阶梯部分,多个第一导电层的端部的位置在阶梯部分中不同。 半导体层被第一区域中的第一导电层围绕,包括沿堆叠方向延伸的第一柱状部分。 电荷存储层形成在第一导电层与第一柱状部分的侧面之间。 绝缘柱状层被台阶部分的第一导电层包围,并且包括在层叠方向上延伸并包括绝缘体的第二柱状部分。
    • 9. 发明申请
    • NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    • 非易失性半导体存储器件
    • US20110216597A1
    • 2011-09-08
    • US12882512
    • 2010-09-15
    • Kazuyuki HIGASHITadashi Iguchi
    • Kazuyuki HIGASHITadashi Iguchi
    • G11C16/04
    • H01L27/11582G11C16/0483
    • A memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The semiconductor layer includes a columnar portion that extends in a perpendicular direction to a substrate. The charge storage layer is formed around a side surface of the columnar portion. The plurality of first conductive layers are formed around the side surface of the columnar portion and the charge storage layer. A control circuit comprises a plurality of second conductive layers, an insulating layer, and a plurality of plug layers. The plurality of second conductive layers are formed in the same layers as the plurality of first conductive layers. The insulating layer is formed penetrating the plurality of second conductive layers in the perpendicular direction. The plurality of plug layers are formed penetrating the insulating layer in the perpendicular direction. The insulating layer has a rectangular shaped cross-section with a constricted portion in a horizontal direction to the substrate. The constricted portion is positioned on a long side of the cross-section.
    • 存储器串包括半导体层,电荷存储层和多个第一导电层。 半导体层包括沿与基板垂直的方向延伸的柱状部分。 电荷存储层围绕柱状部分的侧表面形成。 多个第一导电层围绕柱状部分和电荷存储层的侧表面形成。 控制电路包括多个第二导电层,绝缘层和多个插塞层。 多个第二导电层形成在与多个第一导电层相同的层中。 绝缘层形成为沿着垂直方向穿过多个第二导电层。 多个插塞层在垂直方向上形成为穿透绝缘层。 绝缘层具有矩形截面,在基板的水平方向上具有缩颈部分。 收缩部分位于横截面的长边上。
    • 10. 发明申请
    • MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
    • 半导体器件的制造方法
    • US20090317978A1
    • 2009-12-24
    • US12487979
    • 2009-06-19
    • Kazuyuki HIGASHI
    • Kazuyuki HIGASHI
    • H01L21/311
    • H01L21/0337H01L21/0338H01L21/31144
    • In one aspect of the present invention, a method of manufacturing semiconductor device may include forming a second core on a member to be processed, and a first core on the second core, the second core located below the first core and having a width larger than that of the first core, forming a coating film on a top surface and side surfaces of the first core, and a top surface and side surfaces of the second core, processing the coating film into sidewall masks by partially removing the coating film in a manner that portions of the coating film, which are located on the side surfaces of the first and second cores, are left remaining, etching the first and second cores by using the sidewall masks as a mask so as to remove the first core and portions of the second core which are not covered with the sidewall masks from above, so that an etching mask including the sidewall masks and portions of the second core which remain directly below the sidewall masks is formed, and etching the member by using the etching mask as a mask, so that the member is patterned.
    • 在本发明的一个方面中,制造半导体器件的方法可以包括在要加工的部件上形成第二芯,在第二芯上形成第一芯,第二芯位于第一芯的下方,其宽度大于 第一芯的第一芯在第一芯的顶表面和侧表面以及第二芯的顶表面和侧表面上形成涂膜,通过以一定程度的部分去除涂膜将涂膜加工成侧壁掩模 位于第一和第二芯的侧表面上的涂膜的部分留下,通过使用侧壁掩模作为掩模蚀刻第一和第二芯,以便去除第一芯和第二芯的部分 第二芯,其不被来自上面的侧壁掩模覆盖,从而形成包括侧壁掩模的蚀刻掩模和保持在侧壁掩模正下方的第二芯的部分,并蚀刻该内存 通过使用蚀刻掩模作为掩模,使得构件被图案化。