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    • 3. 发明授权
    • Decoding device and method
    • 解码设备和方法
    • US08166363B2
    • 2012-04-24
    • US12066641
    • 2006-09-07
    • Osamu ShinyaTakashi YokokawaYuji ShinoharaToshiyuki Miyauchi
    • Osamu ShinyaTakashi YokokawaYuji ShinoharaToshiyuki Miyauchi
    • H03M13/00
    • H04L1/0052H03M13/1111H03M13/118H03M13/6577H04L1/0057
    • A decoding device and method for decoding an LDPC code with high accuracy while suppressing an increase of the scale of a device. A check node calculator (181) performs check node calculations including calculations of a nonlinear function φ(x) and its inverse function φ−1(x) of the nonlinear function so as to decode an LDPC code. A variable node calculator (103) performs variable node calculation of a variable node so as to decode the LDPC code. The check node calculator (181) has an LUT which receives a fixed-point quantized value expressing a numerical value with a fixed quantization width and outputs the result of the calculation of the nonlinear function φ(x) as a semi-floating point quantized value which is a bit sequence expressing a numerical value with a quantization width determined by a part of a bit sequence and an LUT which receives a semi-floating point quantized value and outputs the result of the calculation of the inverse function φ−1(x) as a fixed point quantized value. The invention can be applied to e.g., a tuner for receiving a satellite broadcast.
    • 一种用于在抑制设备规模增加的同时高精度地解码LDPC码的解码装置和方法。 校验节点计算器(181)执行包括非线性函数的计算的校验节点计算(x)及其非线性函数的反函数&phgr(-1),以解码LDPC码。 可变节点计算器(103)执行变量节点的可变节点计算,以解码LDPC码。 校验节点计算器(181)具有LUT,其接收表示具有固定量化宽度的数值的定点量化值,并将非线性函数&(x)的计算结果作为半浮点数量化 值,其是表示具有由位序列的一部分确定的量化宽度的数值的位序列和接收半浮点量化值的LUT,并输出反函数的计算结果&phgr; -1( x)作为固定点量化值。 本发明可以应用于例如用于接收卫星广播的调谐器。
    • 5. 发明申请
    • Decoding Device and Method
    • 解码设备和方法
    • US20090304111A1
    • 2009-12-10
    • US12066641
    • 2006-09-07
    • Osamu ShinyaTakashi YokokawaYuji ShinoharaToshiyuki Miyauchi
    • Osamu ShinyaTakashi YokokawaYuji ShinoharaToshiyuki Miyauchi
    • H03K9/00
    • H04L1/0052H03M13/1111H03M13/118H03M13/6577H04L1/0057
    • A decoding device and method for decoding an LDPC code with high accuracy while suppressing an increase of the scale of a device. A check node calculator (181) performs check node calculations including calculations of a nonlinear function φ(x) and its inverse function φ−1(x) of the nonlinear function so as to decode an LDPC code. A variable node calculator (103) performs variable node calculation of a variable node so as to decode the LDPC code. The check node calculator (181) has an LUT which receives a fixed-point quantized value expressing a numerical value with a fixed quantization width and outputs the result of the calculation of the nonlinear function φ(x) as a semi-floating point quantized value which is a bit sequence expressing a numerical value with a quantization width determined by a part of a bit sequence and an LUT which receives a semi-floating point quantized value and outputs the result of the calculation of the inverse function φ−1(x) as a fixed point quantized value. The invention can be applied to e.g., a tuner for receiving a satellite broadcast.
    • 一种用于在抑制设备规模增加的同时高精度地解码LDPC码的解码装置和方法。 校验节点计算器(181)执行包括非线性函数phi(x)及其反函数phi-1(x)的计算的校验节点计算,以解码LDPC码。 可变节点计算器(103)执行变量节点的可变节点计算,以解码LDPC码。 校验节点计算器(181)具有LUT,其接收具有固定量化宽度的表示数值的定点量化值,并将非线性函数phi(x)的计算结果输出为半浮点量化值 其是表示具有由位序列的一部分确定的量化宽度的数值的位序列和接收半浮点量化值的LUT,并输出反函数phi-1(x)的计算结果, 作为固定点量化值。 本发明可以应用于例如用于接收卫星广播的调谐器。
    • 9. 发明申请
    • Decoding Apparatus and Decoding Method
    • 解码装置和解码方法
    • US20090217121A1
    • 2009-08-27
    • US11912481
    • 2006-04-20
    • Takashi YokokawaToshiyuki MiyauchiOsamu Shinya
    • Takashi YokokawaToshiyuki MiyauchiOsamu Shinya
    • H03M13/05G06F11/10
    • H03M13/1168H03M13/1114H03M13/1137H03M13/116H03M13/6505H03M13/6566
    • The present invention relates to a decoding apparatus and a decoding method, which are capable of decoding LDPC codes with a high degree of precision while preventing the circuit scale of the decoding apparatus from increasing. A computation section 1102 carries out a first computation process corresponding to three check-node processes by making use of decoding intermediate results D1101 supplied from a decoding intermediate result storage memory 1104 by way of a cyclic shift circuit 1101, and stores the result of the first computation process in a decoding intermediate result storage memory 1103. A computation section 415 carries out a second computation process corresponding to six variable-node processes by making use of decoding intermediate results D414 supplied from a decoding intermediate result storage memory 1103 by way of a cyclic shift circuit, and stores the decoding intermediate result D415 in the decoding intermediate result storage memory 1104. The present invention can be applied to, for example, a tuner for receiving (digital) satellite broadcasts.
    • 解码装置和解码方法技术领域本发明涉及一种能够在防止解码装置的电路规模增大的同时高精度地解码LDPC码的解码装置和解码方法。 计算部分1102通过利用通过循环移位电路1101从解码中间结果存储存储器1104提供的解码中间结果D1101来执行与三个校验节点处理相对应的第一计算处理,并且存储第一 在解码中间结果存储存储器1103中的计算处理。计算部415通过利用从解码中间结果存储存储器1103提供的解码中间结果D414通过循环的方式执行与六个可变节点处理相对应的第二计算处理 并将解码中间结果D415存储在解码中间结果存储存储器1104中。本发明可以应用于例如用于接收(数字)卫星广播的调谐器。
    • 10. 发明申请
    • DECODING DEVICE AND METHOD, RECEIVING DEVICE AND METHOD, AND PROGRAM
    • 解码设备和方法,接收设备和方法以及程序
    • US20090190695A1
    • 2009-07-30
    • US12361199
    • 2009-01-28
    • Takashi YokokawaYasuhiro IidaToshiyuki MiyauchiTakashi HagiwaraTakanori MinaminoNaoya Haneda
    • Takashi YokokawaYasuhiro IidaToshiyuki MiyauchiTakashi HagiwaraTakanori MinaminoNaoya Haneda
    • H03D3/00
    • H04L27/3827H04L1/0054H04L1/208H04L7/042
    • Disclosed herein is a decoding device that decodes demodulated data obtained by demodulating a quadrature modulated signal arising from digital modulation of a carrier and detects synchronization, the decoding device including, a decoder configured to decode first demodulated data that is the demodulated data obtained by demodulating the quadrature modulated signal and is composed of in-phase axis data and quadrature axis data, and decode second demodulated data obtained by interchanging the in-phase axis data and the quadrature axis data of the first demodulated data, and a synchronization detector configured to detect a boundary between predetermined information symbol sequences from first decoded data obtained by decoding the first demodulated data and detect the boundary from second decoded data obtained by decoding the second demodulated data, the synchronization detector selecting and outputting one of the first decoded data and the second decoded data based on a result of the detection of the boundary.
    • 本文公开了一种解码装置,其对通过解调由载波的数字调制产生的正交调制信号而获得的解调数据进行解码,并检测同步,该解码装置包括:解码器,被配置为对作为解调数据的第一解调数据进行解码, 正交调制信号,并且由同相轴数据和正交轴数据组成,并且对通过交换同相轴数据和第一解调数据的正交轴数据而获得的第二解调数据进行解码,以及同步检测器, 从通过对第一解调数据进行解码而获得的第一解码数据的预定信息符号序列之间的边界,并通过对第二解调数据进行解码获得的第二解码数据检测边界,同步检测器选择并输出第一解码数据和第二解码数据之一 基于de的结果 切割边界。