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1. 发明申请

US20190070076A1 WET SHEET PACKAGE 审中-公开
公开(公告)号：US20190070076A1
公开(公告)日：2019-03-07
申请号：US16077248
申请日：2017-03-31
申请人： Yuji SHINOHARA , GLIDE ENTERPRISE INC
发明人： Yuji SHINOHARA
IPC分类号： A61K8/02 , B65D75/58 , B65D77/04
摘要： Wet-sheet packaging eliminates troubles a user encounters in spreading out a wet sheet after the wet sheet is taken out of the packaging, thereby improving convenience in using the wet sheet. A layered body of folded wet sheets is accommodated in an inner container inside an outer bag that is provided with an outer take-out opening at its surface. The outer take-out opening is freely opened and closed by a closure sheet. The layered body allows a user to grasp an edge of the upper surface of the topmost wet sheet and to spread out the wet sheet. The layered body is made by stacking multiple wet sheets, each of which is folded into a zigzag shape, forming a band-shaped folded body. The edge is disposed at the middle part of the folded body in the width direction facing the lengthwise direction.

2. 发明授权

US09135108B2 Data processing device and data processing method 有权
标题翻译：数据处理装置和数据处理方法
公开(公告)号：US09135108B2
公开(公告)日：2015-09-15
申请号：US14116231
申请日：2012-06-08
申请人： Yuji Shinohara , Makiko Yamamoto
发明人： Yuji Shinohara , Makiko Yamamoto
IPC分类号： G06F11/10 , H03M13/03 , H03M13/11 , H03M13/25 , H03M13/27 , H03M13/29 , H03M13/15 , H04L1/00 , H04L27/36 , H04L27/38 , H03M13/35 , H03M13/00
CPC分类号： G06F11/10 , H03M13/036 , H03M13/1165 , H03M13/1168 , H03M13/152 , H03M13/255 , H03M13/271 , H03M13/2906 , H03M13/2945 , H03M13/356 , H03M13/6552 , H04L1/0047 , H04L1/0057 , H04L27/36 , H04L27/38
摘要： The present technique relates to a data processing device and a data processing method that enable resistance to error of data to be improved.In the case in which an LDPC code having a code length of 16200 bits and an encoding rate of 8/15 is mapped to 16 signal points, if (#i+1)-th bits from most significant bits of sign bits of 4×2 bits and symbol bits of 4×2 bits of two consecutive symbols are set to bits b#i and y#i, respectively, a demultiplexer performs interchanging to allocate b0, b1, b2, b3, b4, b5, b6, and b7 to y0, y4, y3, y1, y2, y5, y6, and y7, respectively. The present technique can be applied to a transmission system or the like transmitting an LDPC code.
摘要翻译：本技术涉及能够提高数据的误差抵抗的数据处理装置和数据处理方法。在码长为16200比特，编码速率为8/15的LDPC码被映射到16个信号点的情况下，如果符号位的最高有效位为4×（＃i + 1） 2位和两个连续符号的4×2位的符号位分别被设置为位b＃i和y＃i，解复用器执行交换以分配b0，b1，b2，b3，b4，b5，b6和b7 分别为y0，y4，y3，y1，y2，y5，y6和y7。本技术可以应用于发送LDPC码的传输系统等。

3. 发明授权

US09106263B2 Data processing device and data processing method 有权
标题翻译：数据处理装置和数据处理方法
公开(公告)号：US09106263B2
公开(公告)日：2015-08-11
申请号：US13883118
申请日：2011-11-29
申请人： Makiko Yamamoto , Yuji Shinohara
发明人： Makiko Yamamoto , Yuji Shinohara
IPC分类号： H03M13/00 , H03M13/13 , H03M13/03 , H03M13/11 , H03M13/25 , H03M13/27 , H03M13/29 , H03M13/35 , H03M13/15
CPC分类号： H03M13/13 , H03M13/033 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/2707 , H03M13/2906 , H03M13/356
摘要： Data processing devices and data process methods that can increase tolerance for data errors. An LDPC encoder performs encoding with an LDPC code having the code length of 16200 bits and one of the six code rates of 1/5, 1/3, 2/5, 4/9, 3/5, and 2/3. The parity check matrix H of the LDPC code is formed by arranging the elements “1” of an information matrix in the column direction in 360-column cycles, the information matrix corresponding to the information length of the parity check matrix H, the information length corresponding to the code length and the code rate, the information matrix being defined by a check matrix initial value table that shows the positions of the elements “1” of the information matrix at intervals of 360 columns. The check matrix initial value table is designed for digital broadcasting intended for portable terminals, for example. The present invention can be applied to cases where LDPC encoding and LDPC decoding are performed.
摘要翻译：可以增加数据错误容限的数据处理设备和数据处理方法。 LDPC编码器使用码长为16200比特和六分之一码率为1/5，1/3，2 / 5,4 / 9,3 / 5和2/3的LDPC码执行编码。 LDPC码的奇偶校验矩阵H通过在列方向上以360列循环布置信息矩阵的元素“1”，形成与奇偶校验矩阵H的信息长度对应的信息矩阵，信息长度对应于代码长度和码率，信息矩阵由以360列的间隔显示信息矩阵的元素“1”的位置的校验矩阵初始值表定义。检查矩阵初始值表例如被设计用于便携式终端的数字广播。本发明可以应用于执行LDPC编码和LDPC解码的情况。

4. 发明授权

US09071276B2 Data-processing device and data-processing method 有权
标题翻译：数据处理设备和数据处理方法
公开(公告)号：US09071276B2
公开(公告)日：2015-06-30
申请号：US13997695
申请日：2012-01-12
申请人： Yuji Shinohara , Makiko Yamamoto
发明人： Yuji Shinohara , Makiko Yamamoto
IPC分类号： H03M13/00 , H03M13/13 , H04L1/00 , H03M13/03 , H03M13/11 , H03M13/25 , H03M13/27 , H03M13/29 , H03M13/35 , H03M13/15 , H04L27/34
CPC分类号： H03M13/13 , H03M13/036 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/2707 , H03M13/271 , H03M13/2906 , H03M13/356 , H03M13/6552 , H04L1/0041 , H04L1/0045 , H04L1/0057 , H04L1/0058 , H04L27/34
摘要： The present technology relates to a data-processing device and a data-processing method, which are capable of improving tolerance for an error of data.When an LDPC code having a code length of 16200 bits is mapped to 16 signal points, a demultiplexer performs exchanging such that when a (#i+1)-th bit from a most significant bit of code bits of 4×2 bits and a (#i+1)-th bit from a most significant bit of symbol bits of 4×2 bits of 2 consecutive symbols are represented by a bit b#i and a bit y#i, respectively, for LDPC codes having coding rates of 1/5, 4/15, and 1/3, b0 is allocated to y4, b1 is allocated to y3, b2 is allocated to y2, b3 is allocated to y1, b4 is allocated to y6, b5 is allocated to y5, b6 is allocated to y7, and b7 is allocated to y0. For example, the present invention can be applied to a transmission system that transmits an LDPC code or the like.
摘要翻译：本技术涉及能够提高数据误差容限的数据处理装置和数据处理方法。当具有16200比特的码长的LDPC码被映射到16个信号点时，解复用器进行交换，使得当从4×2比特的码比特的最高有效比特和第（i + 1）比特的第对于具有编码率的LDPC码，分别由位b＃i和位y＃i表示来自2个连续符号的4×2位的最高有效位的第（i + 1）比特 1/5,4 / 15和1/3，b0分配给y4，b1分配给y3，b2分配给y2，b3分配给y1，b4分配给y6，b5分配给y5，b6 分配给y7，b7分配给y0。例如，本发明可以应用于发送LDPC码等的发送系统。

5. 发明申请

US20130166992A1 DATA PROCESSING DEVICE AND DATA PROCESSING METHOD 有权
标题翻译：数据处理设备和数据处理方法
公开(公告)号：US20130166992A1
公开(公告)日：2013-06-27
申请号：US13820808
申请日：2011-09-09
申请人： Yuji Shinohara , Makiko Yamamoto , Lui Sakai
发明人： Yuji Shinohara , Makiko Yamamoto , Lui Sakai
IPC分类号： H03M13/13
CPC分类号： H03M13/13 , H03M13/036 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/2707 , H03M13/271 , H03M13/2906 , H03M13/356 , H03M13/6552
摘要： The present invention relates to a data processing device and a data processing method capable of improving the resistance to data error. In a case where an LDPC code having a code length of 4,320 bits is mapped into 16 signal points, when a code bit of 4×2 bits and the (#i+1)-th bit from the most significant bit of symbol bits of 4×2 bits of two consecutive symbols are bits b#i and y#i, a demultiplexer performs an interchange process in which b0 is allocated to y0, b1 is allocated to y4, b2 is allocated to y1, b3 is allocated to y6, b4 is allocated to y2, b5 is allocated to y5, b6 is allocated to y3, and b7 is allocated to y7 for an LDPC code having a coded rate of 1/2, and b0 is allocated to y0, b1 is allocated to y4, b2 is allocated to y5, b3 is allocated to y2, b4 is allocated to y1, b5 is allocated to y6, b6 is allocated to y3, and b7 is allocated to y7 for an LDPC code having a coded rate of 7/12, 2/3, and 3/4. The present invention, for example, can be applied to a transmission system transmitting an LDPC code and the like.
摘要翻译：本发明涉及能够提高数据误差阻力的数据处理装置和数据处理方法。在具有4,320比特的码长的LDPC码被映射到16个信号点的情况下，当4×2比特的码比特和来自符号比特的最高有效位的（＃i + 1）比特两个连续符号的4×2位是位b＃i和y＃i，解复用器执行其中b0被分配给y0的交换处理，b1被分配给y4，b2被分配给y1，b3被分配给y6，将b4分配给y2，将b5分配给y5，将b6分配给y3，将b7分配给y7，对于编码速率为1/2的LDPC码，将b0分配给y0，将b1分配给y4， b2分配给y5，b3分配给y2，b4分配给y1，b5分配给y6，b6分配给y3，b7分配给y7，对于编码率为7/12的LDPC码，2 / 3和3/4。本发明例如可以应用于传输LDPC码等的传输系统。

6. 发明申请

US20120132267A1 Photoelectric conversion device and electronic equipment 有权
标题翻译：光电转换装置及电子设备
公开(公告)号：US20120132267A1
公开(公告)日：2012-05-31
申请号：US12007960
申请日：2008-01-17
申请人： Yuji Shinohara , Yoshiharu Ajiki , Katsuya Teshima , Shuji Oishi
发明人： Yuji Shinohara , Yoshiharu Ajiki , Katsuya Teshima , Shuji Oishi
IPC分类号： H01L31/0224 , H01L31/04
CPC分类号： H01G9/2031 , H01G9/2027 , H01G9/2036 , H01G9/2059 , Y02E10/542
摘要： A photoelectric conversion device provided with an electron transport layer having an excellent electron transport ability and having an excellent photoelectric conversion efficiency, and electronic equipment provided with such a photoelectric conversion device and having a high reliability are provided. A solar cell, to which the photoelectric conversion device is applied, has a first electrode provided on a substrate, a second electrode arranged opposite to the first electrode and retained on a facing substrate, an electron transport layer provided between these electrodes and positioned on the side of the first electrode, a dye layer being in contact with the electron transport layer, and an electrolyte layer provided between the electron transport layer and the second electrode and being in contact with the dye layer. The electron transport layer is constituted of a monocrystalline material of multiple oxide as a main component thereof. Further, it is preferred that the monocrystalline material of multiple oxide has a layer structure in a crystal structure thereof.
摘要翻译：提供具有电子传输能力优异并且具有优异的光电转换效率的电子传输层的光电转换装置和具有这种光电转换装置并具有高可靠性的电子设备。设置有光电转换装置的太阳能电池具有设置在基板上的第一电极，与第一电极相对设置并保持在面对基板上的第二电极，设置在这些电极之间并位于其上的电子传输层第一电极的侧面，与电子传输层接触的染料层，以及设置在电子传输层和第二电极之间并与染料层接触的电解质层。电子传输层由作为其主要成分的多种氧化物的单晶材料构成。此外，优选多个氧化物的单晶材料具有其晶体结构中的层结构。

7. 发明授权

US08166363B2 Decoding device and method 失效
标题翻译：解码设备和方法
公开(公告)号：US08166363B2
公开(公告)日：2012-04-24
申请号：US12066641
申请日：2006-09-07
申请人： Osamu Shinya , Takashi Yokokawa , Yuji Shinohara , Toshiyuki Miyauchi
发明人： Osamu Shinya , Takashi Yokokawa , Yuji Shinohara , Toshiyuki Miyauchi
IPC分类号： H03M13/00
CPC分类号： H04L1/0052 , H03M13/1111 , H03M13/118 , H03M13/6577 , H04L1/0057
摘要： A decoding device and method for decoding an LDPC code with high accuracy while suppressing an increase of the scale of a device. A check node calculator (181) performs check node calculations including calculations of a nonlinear function φ(x) and its inverse function φ−1(x) of the nonlinear function so as to decode an LDPC code. A variable node calculator (103) performs variable node calculation of a variable node so as to decode the LDPC code. The check node calculator (181) has an LUT which receives a fixed-point quantized value expressing a numerical value with a fixed quantization width and outputs the result of the calculation of the nonlinear function φ(x) as a semi-floating point quantized value which is a bit sequence expressing a numerical value with a quantization width determined by a part of a bit sequence and an LUT which receives a semi-floating point quantized value and outputs the result of the calculation of the inverse function φ−1(x) as a fixed point quantized value. The invention can be applied to e.g., a tuner for receiving a satellite broadcast.
摘要翻译：一种用于在抑制设备规模增加的同时高精度地解码LDPC码的解码装置和方法。校验节点计算器（181）执行包括非线性函数的计算的校验节点计算（x）及其非线性函数的反函数＆phgr（-1），以解码LDPC码。可变节点计算器（103）执行变量节点的可变节点计算，以解码LDPC码。校验节点计算器（181）具有LUT，其接收表示具有固定量化宽度的数值的定点量化值，并将非线性函数＆amp;（x）的计算结果作为半浮点数量化值，其是表示具有由位序列的一部分确定的量化宽度的数值的位序列和接收半浮点量化值的LUT，并输出反函数的计算结果＆phgr; -1（ x）作为固定点量化值。本发明可以应用于例如用于接收卫星广播的调谐器。

8. 发明申请

US20110229748A1 CYLINDRICAL SECONDARY BATTERY AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：圆柱二次电池及其制造方法
公开(公告)号：US20110229748A1
公开(公告)日：2011-09-22
申请号：US13051450
申请日：2011-03-18
申请人： Hiromasa Sugii , Makoto Ochi , Ryu Yamashita , Yuji Shinohara , Akira Nishida , Yu Matsui , Atutoshi Ako , Kazuhiro Kitaoka
发明人： Hiromasa Sugii , Makoto Ochi , Ryu Yamashita , Yuji Shinohara , Akira Nishida , Yu Matsui , Atutoshi Ako , Kazuhiro Kitaoka
IPC分类号： H01M6/02 , H01M10/04 , H01M4/00 , H01M2/02 , H01M2/18
CPC分类号： H01M2/263 , H01M2/0413 , H01M2/1276 , H01M10/0422 , H01M10/286 , Y10T29/4911
摘要： The current-collecting lead for being welded to a collector welded to an upper portion of an electrode group and also to a sealing assembly of an cylindrical secondary battery includes: a flat surface part welded to the collector, and a top part formed to be curved and protrude approximately in the shape of a dome from the flat surface part and welded to the sealing assembly. A central opening is formed at a central portion of the top part. Around the central opening, a plurality of welding projections are formed to protrude toward the sealing assembly. The welding projections serve as welding spots to the sealing assembly. The top part is deformed by a pressing force from the sealing assembly to be brought into surface contact with a corner portion of a convex portion formed on a lower surface of the sealing assembly.
摘要翻译：用于焊接到焊接到电极组的上部的集电体的集电引线以及圆柱形二次电池的密封组件包括：焊接到集电器的平坦表面部分和形成为弯曲的顶部并且从平坦表面部分大致突出成圆顶形状并焊接到密封组件。中央开口形成在顶部的中心部分。围绕中心开口形成有多个焊接突起朝向密封组件突出。焊接突起用作密封组件的焊接点。顶部通过来自密封组件的压力而变形，以与形成在密封组件的下表面上的凸部的角部进行表面接触。

9. 发明申请

US20090304111A1 Decoding Device and Method 失效
标题翻译：解码设备和方法
公开(公告)号：US20090304111A1
公开(公告)日：2009-12-10
申请号：US12066641
申请日：2006-09-07
申请人： Osamu Shinya , Takashi Yokokawa , Yuji Shinohara , Toshiyuki Miyauchi
发明人： Osamu Shinya , Takashi Yokokawa , Yuji Shinohara , Toshiyuki Miyauchi
IPC分类号： H03K9/00
CPC分类号： H04L1/0052 , H03M13/1111 , H03M13/118 , H03M13/6577 , H04L1/0057
摘要： A decoding device and method for decoding an LDPC code with high accuracy while suppressing an increase of the scale of a device. A check node calculator (181) performs check node calculations including calculations of a nonlinear function φ(x) and its inverse function φ−1(x) of the nonlinear function so as to decode an LDPC code. A variable node calculator (103) performs variable node calculation of a variable node so as to decode the LDPC code. The check node calculator (181) has an LUT which receives a fixed-point quantized value expressing a numerical value with a fixed quantization width and outputs the result of the calculation of the nonlinear function φ(x) as a semi-floating point quantized value which is a bit sequence expressing a numerical value with a quantization width determined by a part of a bit sequence and an LUT which receives a semi-floating point quantized value and outputs the result of the calculation of the inverse function φ−1(x) as a fixed point quantized value. The invention can be applied to e.g., a tuner for receiving a satellite broadcast.
摘要翻译：一种用于在抑制设备规模增加的同时高精度地解码LDPC码的解码装置和方法。校验节点计算器（181）执行包括非线性函数phi（x）及其反函数phi-1（x）的计算的校验节点计算，以解码LDPC码。可变节点计算器（103）执行变量节点的可变节点计算，以解码LDPC码。校验节点计算器（181）具有LUT，其接收具有固定量化宽度的表示数值的定点量化值，并将非线性函数phi（x）的计算结果输出为半浮点量化值其是表示具有由位序列的一部分确定的量化宽度的数值的位序列和接收半浮点量化值的LUT，并输出反函数phi-1（x）的计算结果，作为固定点量化值。本发明可以应用于例如用于接收卫星广播的调谐器。

10. 发明申请

US20080252566A1 Display, Display Method, and Electronic Device 有权
标题翻译：显示，显示方式和电子设备
公开(公告)号：US20080252566A1
公开(公告)日：2008-10-16
申请号：US12043698
申请日：2008-03-06
申请人： Takeo KAWASE , Takayuki KONDO , Hitoshi FUKUSHIMA , Yuji SHINOHARA
发明人： Takeo KAWASE , Takayuki KONDO , Hitoshi FUKUSHIMA , Yuji SHINOHARA
IPC分类号： G09G3/30
CPC分类号： G09G3/3446 , G02F1/167 , G02F2203/34
摘要： A display, comprising: a planar display section; a pixel space provided next to a side adjacent to one surface of the display section and encapsulating a plurality of kinds of colorants, each kind having a different color; an accumulation section provided in the pixel space and accumulating the colorants; a separation system that separates a specific kind of colorant from the accumulated colorants in the accumulation section; a transfer system that selects at least one kind of colorant from the separated colorants and transfers this colorant to the side adjacent to the display section of the pixel space. The separation system performs separation utilizing the magnitude of a dielectrophoretic force generated in each colorant upon receipt of an alternating electric field of a specific frequency applied by this system, the magnitude varying depending on the kind of the colorant. A color of at least the one kind of colorant transferred by the transfer system is displayed at the display section.
摘要翻译：一种显示器，包括：平面显示部分; 设置在与显示部的一个表面相邻的一侧的像素空间，并且封装多种着色剂，每种着色剂具有不同的颜色; 设置在像素空间中并累积着色剂的累积部分; 分离系统，其将特定种类的着色剂与累积部分中的累积着色剂分离; 转移系统，其从分离的着色剂中选择至少一种着色剂并将该着色剂转移到与像素空间的显示部分相邻的一侧。分离系统在接收到由该系统施加的特定频率的交变电场时，利用每种着色剂中产生的介电电泳力的大小进行分离，其大小根据着色剂的种类而变化。在显示部分显示至少一种由转印系统转印的着色剂的颜色。

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