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1. 发明授权

US06303495B2 Method of forming thin copper film and semiconductor device with thin copper film 失效
标题翻译：铜薄膜形成方法及铜薄膜半导体器件
公开(公告)号：US06303495B2
公开(公告)日：2001-10-16
申请号：US09038117
申请日：1998-03-11
申请人： Takeshi Mori , Tetsuo Fukada , Makiko Hasegawa , Yoshihiko Toyoda
发明人： Takeshi Mori , Tetsuo Fukada , Makiko Hasegawa , Yoshihiko Toyoda
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , C23C16/0272 , C23C16/18 , H01L21/32051 , H01L21/76858 , H01L21/76876
摘要： Copper material is exposed on the surface of a TiN film (an underlying film) formed in the main surface of a silicon substrate with a silicon oxide film interposed. Subsequently, a thin copper film is formed on TiN film. Thus, the thin copper film can be formed on the film including metal with high melting point or nitride thereof with high adhesion by means of CVD.
摘要翻译：在硅衬底的主表面上形成有氧化硅膜的TiN膜（底层膜）的表面上露出铜材料。随后，在TiN膜上形成薄的铜膜。因此，可以通过CVD在具有高熔点的金属或其氮化物的膜上形成具有高粘附性的薄膜。

2. 发明授权

US06184124B2 Method of making embedded wiring system 失效
标题翻译：嵌入式布线系统的制作方法
公开(公告)号：US06184124B2
公开(公告)日：2001-02-06
申请号：US09078510
申请日：1998-05-14
申请人： Makiko Hasegawa , Yoshihiko Toyoda , Takeshi Mori , Tetsuo Fukada
发明人： Makiko Hasegawa , Yoshihiko Toyoda , Takeshi Mori , Tetsuo Fukada
IPC分类号： H01L214763
CPC分类号： H01L21/76849 , H01L21/76844 , H01L21/76847 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of preparing a multilevel embedded wiring system for an IC comprising a first wiring formation step, a first connecting portion formation step, and a second wiring formation step, wherein the first wiring formation step comprises forming a first trench for a first embedded wiring in a first insulating layer disposed on a substrate and embedding in the first trench, in turn, a first conductive layer and a first conductive capping layer; the first connecting portion formation step comprises forming a second insulating layer on the first insulating layer and the first conductive capping layer, forming a via-hole in a part of the second insulating layer at the first conductive capping layer, and embedding a conductive connecting portion in the via-hole and connected to the first conductive layer; and the second formation step comprises forming a third insulating layer on the second insulating layer and the conductive connecting portion, forming a second trench for a second wiring in the third insulating layer at the conductive connecting portion, and embedding a second conductive layer in the second trench and connected to the conductive connecting portion.
摘要翻译：一种制备用于IC的多层嵌入式布线系统的方法，包括：第一布线形成步骤，第一连接部分形成步骤和第二布线形成步骤，其中所述第一布线形成步骤包括：形成用于第一嵌入布线的第一沟槽第一绝缘层，设置在基板上并嵌入第一沟槽中，依次具有第一导电层和第一导电覆盖层; 第一连接部分形成步骤包括在第一绝缘层和第一导电覆盖层上形成第二绝缘层，在第一导电覆盖层的第二绝缘层的一部分中形成通孔，并且将导电连接部分在所述通孔中并连接到所述第一导电层; 并且第二形成步骤包括在第二绝缘层和导电连接部分上形成第三绝缘层，在导电连接部分处在第三绝缘层中形成用于第二布线的第二沟槽，并在第二绝缘层中嵌入第二导电层沟槽并连接到导电连接部分。

3. 发明授权

US5793112A Multilevel embedded wiring system 失效
标题翻译：多层嵌入式布线系统
公开(公告)号：US5793112A
公开(公告)日：1998-08-11
申请号：US715446
申请日：1996-09-18
申请人： Makiko Hasegawa , Yoshihiko Toyoda , Takeshi Mori , Tetsuo Fukada
发明人： Makiko Hasegawa , Yoshihiko Toyoda , Takeshi Mori , Tetsuo Fukada
IPC分类号： H01L21/3205 , H01L23/52 , H01L23/532 , H01L23/538 , H01L23/48 , H01L29/40
CPC分类号： H01L21/76849 , H01L21/76844 , H01L21/76847 , H01L23/53233 , H01L23/53238 , H01L2924/0002
摘要： The multilevel embedded wiring system for an IC has a capping layer on the conductive layer in channels or trenches in insulating layers. The capping layer prevents halation of light in a lithography process, resulting in a high precision structure. Even if Cu is used as the conductive material, the resulting wiring resistivity is still low and the diffusion and oxidation of Cu are prevented.
摘要翻译：用于IC的多电平嵌入式布线系统在绝缘层中的通道或沟槽中的导电层上具有覆盖层。封盖层防止光刻过程中的光晕，导致高精度结构。即使使用Cu作为导电材料，所得的布线电阻率仍然较低，并且防止了Cu的扩散和氧化。

4. 发明授权

US6039808A CVD apparatus for Cu formation 失效
标题翻译： Cu形成用CVD装置
公开(公告)号：US6039808A
公开(公告)日：2000-03-21
申请号：US42693
申请日：1998-03-17
申请人： Yoshihiko Toyoda , Tetsuo Fukada , Takeshi Mori , Makiko Hasegawa
发明人： Yoshihiko Toyoda , Tetsuo Fukada , Takeshi Mori , Makiko Hasegawa
IPC分类号： C23C16/14 , C23C16/18 , C23C16/44 , H01L21/205 , H01L21/285 , C23C16/06
CPC分类号： C23C16/4404 , C23C16/18
摘要： In a CVD apparatus for Cu formation using as a raw material, a mixture of a solvent and a liquid raw material including Cu(HFA) and adducted molecules or a solid raw material including Cu(HFA) and adducted molecules, a fluorinated organic polymer contained, a fluorinated metal, an insulator or a Ti compound is provided on a surface of a member at a portion where the raw material exists.
摘要翻译：在作为原料的Cu形成用CVD装置中，溶剂和包含Cu（HFA）和加合分子的液体原料或包含Cu（HFA）和加成分子的固体原料的混合物含有含氟有机聚合物在原料存在的部分的表面上设置氟化金属，绝缘体或Ti化合物。

5. 发明授权

US6107687A Semiconductor device having interconnection and adhesion layers 失效
标题翻译：具有互连和粘附层的半导体器件
公开(公告)号：US6107687A
公开(公告)日：2000-08-22
申请号：US39388
申请日：1998-03-16
申请人： Tetsuo Fukada , Takeshi Mori , Makiko Hasegawa , Yoshihiko Toyoda
发明人： Tetsuo Fukada , Takeshi Mori , Makiko Hasegawa , Yoshihiko Toyoda
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/532 , H01L23/48 , H01L29/40
CPC分类号： H01L21/76865 , H01L21/76849 , H01L21/76858 , H01L23/53238 , H01L2924/0002
摘要： A Cu interconnection layer is formed in a trench provided in an insulating layer with a base layer interposed therebetween, an adhesion layer is formed on the Cu interconnection layer and a cap layer is formed on the adhesion layer to restrict exfoliation of the cap layer formed on the Cu interconnection layer buried in the trench formed in the insulating layer.
摘要翻译：在设置在绝缘层中的沟槽中形成Cu互连层，其中介于基底层之间，在Cu互连层上形成粘合层，并且在粘合层上形成覆盖层，以限制形成在其上的覆盖层的剥离所述Cu互连层埋在形成在绝缘层中的沟槽中。

6. 发明授权

US5892286A Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5892286A
公开(公告)日：1999-04-06
申请号：US759999
申请日：1996-12-03
申请人： Yoshihiko Toyoda , Takeshi Mori , Tetsuo Fukada , Makiko Hasegawa
发明人： Yoshihiko Toyoda , Takeshi Mori , Tetsuo Fukada , Makiko Hasegawa
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/3205 , H01L21/768 , H01L23/528 , H01L23/532 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/53233 , H01L21/31116 , H01L21/76816 , H01L23/5283 , H01L23/53223 , H01L2924/0002
摘要： To form a plurality of patterned conductor leads in the same layer of an integrated circuit, an insulating film is etched to form a plurality of patterned grooves by plasma etching using an etching gas containing carbon and fluorine to which an additive gas containing carbon is added. The etching rate is substantially proportional to the groove width, so that the groove depth is substantially proportional to the groove width. Grooves are filled with a conductive material to form patterned conductor leads. Thus, an aspect ratio of the patterned conductor leads is kept in a certain range, resulting in an improvement in yield and reliability of the conductor leads. The conductor leads formed of material containing copper are coated with a diffusion preventive film.
摘要翻译：为了在集成电路的同一层中形成多个图案化的导体引线，通过使用含有碳和氟的蚀刻气体，通过等离子体蚀刻来蚀刻绝缘膜以形成多个图案化的凹槽，添加含有碳的添加气体。蚀刻速率基本上与凹槽宽度成比例，使得凹槽深度基本上与凹槽宽度成比例。沟槽填充有导电材料以形成图案化导体引线。因此，图案化的导体引线的纵横比保持在一定范围内，导致导体引线的产量和可靠性的提高。由含有铜的材料形成的导体引线涂覆有防扩散膜。

7. 发明授权

US06215189B1 Semiconductor device having interconnect layer and method of manufacturing therefor 失效
标题翻译：具有互连层的半导体器件及其制造方法
公开(公告)号：US06215189B1
公开(公告)日：2001-04-10
申请号：US09302290
申请日：1999-04-30
申请人： Yoshihiko Toyoda , Tetsuo Fukada , Takeshi Mori , Yoshiyuki Kitazawa
发明人： Yoshihiko Toyoda , Tetsuo Fukada , Takeshi Mori , Yoshiyuki Kitazawa
IPC分类号： H01L2348
CPC分类号： H01L23/53209 , H01L21/76802 , H01L21/76807 , H01L2924/0002 , H01L2924/00
摘要： A highly reliable semiconductor device having a contact hole with a sufficient area can be obtained. An interlevel insulating film is formed on a conductive region having a first width. A through hole which exposes the conductive region is formed at the interlevel insulating film. A coating film is formed on the interlevel insulating film. In the coating film, an opening having a second width larger than the first width is formed in a region located on the through hole. An interconnect line is formed in a region located on the opening. A conductor film for electrically connecting the conductive region and the interconnect line is generated within the through hole.
摘要翻译：可以获得具有足够面积的接触孔的高度可靠的半导体器件。在具有第一宽度的导电区域上形成层间绝缘膜。在层间绝缘膜上形成露出导电区域的通孔。在层间绝缘膜上形成涂膜。在涂膜中，在位于通孔的区域中形成具有大于第一宽度的第二宽度的开口。在位于开口的区域中形成互连线。在通孔内产生用于电连接导电区域和互连线的导体膜。

8. 发明授权

US06335570B1 Semiconductor device and manufacturing method thereof 有权
公开(公告)号：US06335570B1
公开(公告)日：2002-01-01
申请号：US09293784
申请日：1999-04-20
申请人： Takeshi Mori , Yoshihiko Toyoda , Tetsuo Fukada , Yoshiyuki Kitazawa
发明人： Takeshi Mori , Yoshihiko Toyoda , Tetsuo Fukada , Yoshiyuki Kitazawa
IPC分类号： H01L2348
摘要： A semiconductor device capable of preventing diffusion of a particle of copper or the like which forms a conductive layer is provided without any increase in the number of manufacturing the steps. Further, a semiconductor device preventing diffusion of a particle forming a conductive layer into an insulating layer even when a width of the conductive layer is increased is provided. The semiconductor device includes: an insulating layer 2; a barrier layer 4; a conductive layer 5; a barrier layer 6 having an opening 11; an insulating layer 7 having a through hole 8 exposing a surface of conductive layer 5 and a part of a surface of barrier layer 6; a barrier layer 9 formed on a surface of said through hole 8 and insulating layer 7 which is in contact with an upper surface 6a of barrier layer 6; and a conductive layer 10 filling opening 11 and through hole 8.

9. 发明申请

US20050263770A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050263770A1
公开(公告)日：2005-12-01
申请号：US11137660
申请日：2005-05-26
申请人： Kazuyuki Sugahara , Naoki Nakagawa , Yoshihiko Toyoda , Takao Sakamoto
发明人： Kazuyuki Sugahara , Naoki Nakagawa , Yoshihiko Toyoda , Takao Sakamoto
IPC分类号： H01L51/50 , H01L21/336 , H01L21/77 , H01L21/8234 , H01L21/84 , H01L27/08 , H01L27/088 , H01L27/12 , H01L29/786 , H05B33/14
CPC分类号： H01L27/1222 , H01L27/1214 , H01L27/127 , H01L29/78621 , H01L29/78627
摘要： A first thin film transistor including a gate electrode, a source region, a drain region, a GOLD region, and a channel region is formed at a first region at a TFT array substrate. A second thin film transistor including a gate electrode, a source region, drain region, a GOLD region, and a channel region is formed at a second region. The GOLD length (0.5 μm) of the GOLD region of the second thin film transistor is set shorter than the GOLD length (1.5 μm) of the GOLD region of the first thin film transistor. Accordingly, a semiconductor device directed to reducing the area occupied by semiconductor elements is obtained.
摘要翻译：在TFT阵列基板的第一区域形成包括栅极，源极区，漏极区，GOLD区和沟道区的第一薄膜晶体管。在第二区域形成包括栅电极，源极区，漏极区，GOLD区和沟道区的第二薄膜晶体管。第二薄膜晶体管的GOLD区域的GOLD长度（0.5μm）被设定为比第一薄膜晶体管的GOLD区域的GOLD长度（1.5μm）短。因此，获得了旨在减小半导体元件所占的面积的半导体器件。

10. 发明申请

US20050253195A1 Semiconductor device and image display device 审中-公开
标题翻译：半导体装置及图像显示装置
公开(公告)号：US20050253195A1
公开(公告)日：2005-11-17
申请号：US11109818
申请日：2005-04-20
申请人： Yoshihiko Toyoda , Takao Sakamoto , Kazuyuki Sugahara , Naoki Nakagawa
发明人： Yoshihiko Toyoda , Takao Sakamoto , Kazuyuki Sugahara , Naoki Nakagawa
IPC分类号： H01L27/08 , H01L21/00 , H01L21/336 , H01L21/77 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L27/12 , H01L29/786
CPC分类号： H01L27/127 , H01L27/1214 , H01L29/66757 , H01L29/78621 , H01L29/78645
摘要： A silicon nitride film and a silicon oxide film are formed on a glass substrate. On the silicon oxide film is formed a thin film transistor including a source region, a drain region, a channel region having a predetermined channel length, a GOLD region and an LDD region having an impurity concentration lower than the impurity concentration of the source region, a GOLD region and an LDD region having an impurity concentration lower than the impurity concentration of the drain region, a gate insulation film, and a gate electrode. The gate electrode is formed overlapping with and facing the channel region and the GOLD region. A semiconductor device is obtained, directed to improving source-drain breakdown voltage and AC stress resistance, and achieving desired current property.
摘要翻译：在玻璃基板上形成氮化硅膜和氧化硅膜。在氧化硅膜上形成薄膜晶体管，其包括源极区，漏极区，具有预定沟道长度的沟道区，GOLD区和具有低于源区杂质浓度的杂质浓度的LDD区，具有杂质浓度低于漏区杂质浓度的GOLD区和LDD区，栅极绝缘膜和栅电极。栅电极与沟道区域和金区域重叠并面对沟道区域。获得了一种半导体器件，旨在改善源 - 漏击穿电压和AC抗应力，并实现期望的电流特性。

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