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    • 6. 发明授权
    • Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method
    • 自对准开槽积分型场效应晶体管(AccuFET)结构及方法
    • US08878292B2
    • 2014-11-04
    • US12074280
    • 2008-03-02
    • François HébertMadhur BobdeAnup Bhalla
    • François HébertMadhur BobdeAnup Bhalla
    • H01L29/739
    • H01L29/7828H01L29/0619H01L29/0623H01L29/0847H01L29/41766H01L29/456H01L29/66666
    • This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.
    • 本发明公开了一种设置在半导体衬底中的半导体功率器件。 半导体功率器件包括沟槽栅极,每个沟槽栅极具有在由侧壁间隔物围绕的半导体衬底的顶表面之上延伸的伸出栅极段。 半导体功率器件还包括与基本上平行于沟槽栅极的侧壁间隔开的开口的槽。 粘贴门区段还包括由侧壁间隔物围绕的绝缘材料构成的盖。 阻挡金属层覆盖盖的顶表面并且覆盖在侧壁间隔物上并在槽的顶表面上方延伸。 这些槽填充有与栅极段相同的栅极材料,用作附加栅电极,用于提供向沟槽栅极延伸的耗尽层,借此栅极与沟槽栅极之间的漂移区域完全耗尽栅极 - 漏极 电压Vgs = 0伏。
    • 8. 发明授权
    • Topside structures for an insulated gate bipolar transistor (IGBT) device to achieve improved device performances
    • 用于绝缘栅双极晶体管(IGBT)器件的顶部结构,以实现改进的器件性能
    • US08441046B2
    • 2013-05-14
    • US12925869
    • 2010-10-31
    • Madhur BobdeAnup Bhalla
    • Madhur BobdeAnup Bhalla
    • H01L29/66
    • H01L29/7397H01L29/0696H01L29/402H01L29/66348
    • This invention discloses an insulated gate bipolar transistor (IGBT) device formed in a semiconductor substrate. The IGBT device has a split-shielded trench gate that includes an upper gate segment and a lower shield segment. The IGBT device may further include a dummy trench filled with a dielectric layer disposed at a distance away from the split-shielded trench gate. The IGBT device further includes a body region extended between the split-shielded trench gate and the dummy trench encompassing a source region surrounding the split-shielded trench gate near a top surface of the semiconductor substrate. The IGBT device further includes a heavily doped N region disposed below the body region and above a source-dopant drift region above a bottom body-dopant collector region at a bottom surface of the semiconductor substrate. In an alternative embodiment, the IGBT may include a planar gate with a trench shield electrode.
    • 本发明公开了一种形成在半导体衬底中的绝缘栅双极晶体管(IGBT)器件。 IGBT器件具有分裂屏蔽沟槽栅极,其包括上栅极段和下屏蔽段。 IGBT器件还可以包括填充有离开分屏蔽沟槽栅极一定距离设置的电介质层的虚拟沟槽。 IGBT器件还包括在分屏蔽沟槽栅极和虚拟沟槽之间延伸的体区,其围绕半导体衬底的顶表面附近的分离屏蔽沟槽栅极的源极区域。 所述IGBT器件还包括设置在所述体区域的下方且位于所述半导体衬底的底表面的底体 - 掺杂剂集电极区域上方的源 - 掺杂剂漂移区上方的重掺杂N区域。 在替代实施例中,IGBT可以包括具有沟槽屏蔽电极的平面栅极。
    • 9. 发明申请
    • UNI-DIRECTIONAL TRANSIENT VOLTAGE SUPPRESSOR (TVS)
    • 单向瞬态电压抑制器(TVS)
    • US20130001695A1
    • 2013-01-03
    • US13171037
    • 2011-06-28
    • Lingpeng GuanMadhur BobdeAnup Bhalla
    • Lingpeng GuanMadhur BobdeAnup Bhalla
    • H01L29/78H01L21/336
    • H01L27/0262H01L21/8222H01L27/0255H01L27/0259H01L27/0814H01L27/082
    • An epitaxial layer is supported on top of a substrate. First and second body regions are formed within the epitaxial layer separated by a predetermined lateral distance. Trigger and source regions are formed within the epitaxial layer. A first source region is transversely adjacent the first body region between first and second trigger regions laterally adjacent the first source region and transversely adjacent the first body region. A second source region is located transversely adjacent the second body region between third and fourth trigger regions laterally adjacent the second source region and transversely adjacent the second body region. A third source region is laterally adjacent the fourth trigger region. The fourth trigger region is between the second and third source regions. An implant region within the fourth trigger region is laterally adjacent the third source region.
    • 外延层支撑在基板的顶部。 第一和第二体区域形成在外延层中以预定的横向距离分开。 在外延层内形成触发源区和源极区。 第一源区域横向地邻近第一和第二触发区域之间的与第一源区域相邻并且横向邻近第一体区域的第一体区域相邻。 第二源区域横向地邻近第二和第四触发区域之间的第二体区横向邻近第二源区域并且横向邻近第二体区域定位。 第三源区域与第四触发区域横向相邻。 第四触发区域在第二和第三源区之间。 第四触发区域内的植入区域与第三源区域横向相邻。