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1. 发明公开

US20240305298A1 MANAGING DATA TRANSFERS IN SEMICONDUCTOR DEVICES 审中-公开
公开(公告)号：US20240305298A1
公开(公告)日：2024-09-12
申请号：US18181983
申请日：2023-03-10
申请人： Macronix International Co., Ltd.
发明人： Yi-Fan Chang , Su-Chueh Lo , Jeng-Kuan Lin
IPC分类号： H03K19/0185 , G06F3/06 , G11C7/10 , H03K3/037 , H03K19/00
CPC分类号： H03K19/018521 , G06F3/0604 , G06F3/0656 , G06F3/0679 , G11C7/10 , H03K3/037 , H03K19/0005
摘要： Systems, methods, circuits, and devices for managing data transfers in semiconductor devices are provided. In one aspect, an integrated circuit includes: a first interface for receiving higher-speed-type data, a second interface for receiving lower-speed-type data, a first logic circuit coupled to the first interface, a second logic circuit coupled to the second interface, and a driving circuit separately coupled to the first logic circuit and the second logic circuit. The first data interface, the first logic circuit, and the driving circuit are arranged in series to form a first data path for transferring the higher-speed-type data with a first speed. The second data interface, the second logic circuit, and the driving circuit are arranged in series to form a second data path for transferring the lower-speed-type data with a second speed. The first speed is higher the second speed.

2. 发明授权

US11301151B2 Multi-die memory apparatus and identification method thereof 有权
公开(公告)号：US11301151B2
公开(公告)日：2022-04-12
申请号：US16870848
申请日：2020-05-08
申请人： MACRONIX International Co., Ltd.
发明人： Chun-Hsiung Hung , Su-Chueh Lo
IPC分类号： G06F3/06 , H01L25/065
摘要： A multi-die memory apparatus and identification method thereof are provided. The identification method includes: sending an identification initial command and a first start command to a plurality of memory devices by a controller for starting a first identification period; respectively generating a plurality of first target numbers by the memory devices; respectively performing first counting actions and comparing a plurality of first counting numbers with the first target numbers by a plurality of un-identified memory devices to set a first time-up memory device of the memory devices; and, setting an identification code of the first time-up memory device of the un-identified memory devices to be a first value.

3. 发明授权

US10657051B2 Memory device and operation method thereof 有权
公开(公告)号：US10657051B2
公开(公告)日：2020-05-19
申请号：US15841640
申请日：2017-12-14
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Su-Chueh Lo , Chun-Yu Liao
IPC分类号： G11C16/26 , G06F12/06 , G11C11/417 , G11C11/16 , G11C7/20 , G11C7/10 , G11C11/413 , G11C29/50 , G06F3/06
摘要： Provided is a memory device including: a memory array, including a flag memory array having a plurality of flag memory cells and a data memory array having a plurality of data memory cells, the corresponding flag memory cells being used to record whether the corresponding data memory cells have been written or not. In initialization, the flag memory array is initialized by the control circuit but the data memory array is not initialized.

4. 发明授权

US10289596B2 Memory and method for operating a memory with interruptible command sequence 有权
公开(公告)号：US10289596B2
公开(公告)日：2019-05-14
申请号：US15411731
申请日：2017-01-20
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Ken-Hui Chen , Kuen-Long Chang , Su-Chueh Lo , Chun-Yu Liao
IPC分类号： G06F13/42 , G06F13/16
摘要： A memory device includes command logic allowing for a command protocol allowing interruption of a first command sequence, such as a page write sequence, and then to proceed directly to receive and decode a second command sequence, such as a read sequence, without latency associated, completing the first command sequence. Also, the command logic is configured to be responsive to a third command sequence after the second command sequence and its associated embedded operation have been completed, which completes the interrupted first command sequence and enables execution of an embedded operation identified by the first command sequence. A memory controller supporting such protocols is described.

5. 发明授权

US09450577B1 Circuit with output switch 有权
标题翻译：电路带输出开关
公开(公告)号：US09450577B1
公开(公告)日：2016-09-20
申请号：US14742160
申请日：2015-06-17
申请人： Macronix International Co., Ltd.
发明人： Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Su-Chueh Lo , Tzu-Ting Chiu
IPC分类号： H03K3/00 , H03K17/16
CPC分类号： H03K19/018507
摘要： An output circuit includes: an output switch including a gate terminal, a drain terminal coupled to an external I/O bus, and a well terminal; a well control circuit, having a well terminal coupled to the well terminal of the output switch, to maintain a well voltage of the output switch at a level not less than a greater of a first voltage and a second voltage; and a gate control circuit coupled to the gate terminal and a the drain terminal of the output switch and to the external I/O bus, and operable to turn off the output switch, to prevent current flow through the output switch from the external I/O bus when an operating voltage of the output circuit is not applied to the output switch, and a bus voltage from an external device is present on the external I/O bus.
摘要翻译：输出电路包括：输出开关，包括栅极端子，耦合到外部I / O总线的漏极端子和阱端子; 阱控制电路，具有耦合到输出开关的阱端子的阱端子，以将输出开关的阱电压保持在不小于第一电压和第二电压的较大值的水平; 以及栅极控制电路，其耦合到输出开关的栅极端子和漏极端子和外部I / O总线，并且可操作以关闭输出开关，以防止电流从外部I / O总线流过输出开关， O总线时，输出电路的工作电压不被施加到输出开关，并且来自外部设备的总线电压存在于外部I / O总线上。

6. 发明授权

US08922254B2 Drive circuitry compensated for manufacturing and environmental variation 有权
标题翻译：驱动电路补偿制造和环境变化
公开(公告)号：US08922254B2
公开(公告)日：2014-12-30
申请号：US13913139
申请日：2013-06-07
申请人： Macronix International Co., Ltd.
发明人： Shang-Chi Yang , Ken-Hui Chen , Su-Chueh Lo , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： H03B1/00 , H03K3/00 , H03K17/14
CPC分类号： H03K17/145
摘要： Current drivers and biasing circuitry at least partly compensate for manufacturing variations and environmental variations such as supply voltage, temperature, and fabrication process.
摘要翻译：电流驱动器和偏置电路至少部分地补偿制造变化和环境变化，例如电源电压，温度和制造过程。

7. 发明申请

US20200185010A1 MEMORY CIRCUIT 审中-公开
公开(公告)号：US20200185010A1
公开(公告)日：2020-06-11
申请号：US16534992
申请日：2019-08-07
申请人： MACRONIX International Co., Ltd.
发明人： Su-Chueh Lo , Ken-Hui Chen , Kuen-Long Chang , Ming-Chih Hsieh
IPC分类号： G11C5/14 , G11C7/10 , G11C7/06
摘要： A data receiving stage circuit of a memory circuit receives a serial input signal and a chip enable signal. A data writing circuit of the memory circuit generates at least one of a command signal and a data signal according to the serial input signal. A power supply circuit of the memory circuit generates an operating voltage for a memory cell array to perform a data access operation. A data output stage circuit of the memory circuit outputs a readout data. A controller of the memory circuit performs a switching operation of an operating state of the memory circuit according to a change of the chip enable signal. The controller determines a disable or enable state of the data receiving stage circuit, the data writing circuit, the power supply circuit, and the data output stage circuit according to the operating state.

8. 发明授权

US10620879B2 Write-while-read access method for a memory device 有权
公开(公告)号：US10620879B2
公开(公告)日：2020-04-14
申请号：US15890595
申请日：2018-02-07
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Kuen-Long Chang , Ken-Hui Chen , Su-Chueh Lo , Shang-Chi Yang
IPC分类号： G06F3/06 , G06F12/02 , G06F12/00 , G11C16/10 , G11C7/10 , G11C16/26
CPC分类号： G06F3/0659 , G06F3/0613 , G06F3/0644 , G06F3/0679 , G06F12/00 , G06F12/0246 , G11C7/1042 , G11C16/10 , G11C16/26 , G06F2212/1024 , G06F2212/7201 , G06F2212/7203 , G11C2207/2209
摘要： A memory device includes a memory including first and second pages in first and second banks, respectively, an address decoder mapping command addresses to physical addresses. The memory device further includes circuitry configured to maintain a status indicating a most recently written page, decode received command sequences including command addresses and implementing an operation including (i) responsive to receiving a command sequence including a read command address that is pre-configured for reading data, causing the address decoder to map the read command address to one of the first and second pages selected according to the status, and (ii) responsive to receiving a second command sequence including a write command address that is pre-configured for writing data, causing the address decoder to map the write command address to one of the first and second pages selected according to the status.

9. 发明申请

US20170212696A1 GENERATING A TRANSITION SIGNAL FOR CONTROLLING MEMORY DATA OUTPUT 审中-公开
公开(公告)号：US20170212696A1
公开(公告)日：2017-07-27
申请号：US15006316
申请日：2016-01-26
申请人： Macronix International Co., Ltd.
发明人： Shang-Chi Yang , Su-Chueh Lo
IPC分类号： G06F3/06 , G06F13/40 , G06F13/42 , G06F13/16
CPC分类号： G06F13/4291 , G06F12/0638 , G06F13/1673 , G06F13/28 , G06F13/4022
摘要： A memory device comprises an output buffer and a control circuit. The control circuit is configured to receive a system clock signal at an input of the control circuit. The control circuit is configured to generate a data transition signal based on the system clock signal. The control circuit is configured to provide the data transition signal to the output buffer of the memory device. The output buffer is configured to output memory data based on the data transition signal.

10. 发明申请

US20160072486A1 SENSE AMPLIFIER WITH IMPROVED MARGIN 有权
标题翻译：具有改进标志的感应放大器
公开(公告)号：US20160072486A1
公开(公告)日：2016-03-10
申请号：US14479104
申请日：2014-09-05
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Shang-Chi Yang , Su-Chueh Lo
IPC分类号： H03K5/02 , H01L21/8234 , H01L27/06
CPC分类号： H03K5/023 , G11C7/062 , G11C7/12 , G11C2207/002 , H01L21/8234 , H01L27/0617
摘要： One aspect of the technology is an integrated circuit, comprising a bias circuit and a sense amplifier. The bias circuit has a diode-connected transistor and a first bias voltage. The first bias voltage is represented by a first term inversely dependent on a first mobility of charge carriers of the diode-connected transistor and inversely dependent on a first gate-to-channel dielectric capacitance of the diode-connected transistor. The sense amplifier is coupled to another transistor that has a gate coupled to the first bias voltage of the bias circuit.
摘要翻译：该技术的一个方面是集成电路，包括偏置电路和读出放大器。偏置电路具有二极管连接的晶体管和第一偏置电压。第一偏置电压由与二极管连接的晶体管的电荷载流子的第一迁移率成反比的第一项表示，并且取决于二极管连接晶体管的第一栅极 - 沟道介电电容。读出放大器耦合到具有与偏置电路的第一偏置电压耦合的栅极的另一个晶体管。

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