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1. 发明公开

US20230377633A1 THREE DIMENSION MEMORY DEVICE 审中-公开
公开(公告)号：US20230377633A1
公开(公告)日：2023-11-23
申请号：US17751445
申请日：2022-05-23
申请人： MACRONIX International Co., Ltd.
发明人： Teng-Hao Yeh , Hang-Ting Lue , Shang-Chi Yang , Fu-Nian Liang , Ken-Hui Chen , Chun-Hsiung Hung
IPC分类号： G11C11/4094 , G11C11/408 , G11C11/4096 , G11C11/4072 , G11C11/4091 , G11C11/4093 , G11C5/06
CPC分类号： G11C11/4094 , G11C11/4085 , G11C11/4096 , G11C11/4072 , G11C11/4091 , G11C11/4093 , G11C5/063
摘要： A three dimension memory device, such as an AND-type memory, includes a memory cell tile, multiple source line switches, multiple first bit line switches to fourth bit line switches. The memory cell tile is divided into a first and a second memory cell sub-tiles. The first bit line switches are respectively coupled to multiple first bit lines of a first part of the first memory cell sub-tile. The second bit line switches are respectively coupled to multiple second bit lines of a second part of the first memory cell sub-tile. The third bit line switches are respectively coupled to multiple third bit lines of a first part of the second memory cell sub-tile. The fourth bit line switches are respectively coupled to multiple fourth bit lines of a second part of the second memory cell sub-tile.

2. 发明授权

US11258599B2 Stable physically unclonable function 有权
公开(公告)号：US11258599B2
公开(公告)日：2022-02-22
申请号：US16793986
申请日：2020-02-18
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Shih-Chang Huang , Chin-Hung Chang , Chen-Chia Fan
IPC分类号： H04L9/08 , H04L9/32 , G06F21/62 , G06F3/06 , G06F12/0877
摘要： A system and method use a physical unclonable function in a PUF circuit on an integrated circuit to generate a security key, and stabilize the security key by storage in a set of nonvolatile memory cells. The stabilized security key is moved from the set of nonvolatile memory cells to a cache memory, and utilized as stored in the cache memory in a security protocol. Also, data transfer from the PUF circuit to the set of nonvolatile memory cells can be disabled after using the PUF circuit to produce the security key, at a safe time, such as after the security key has been moved from the set of nonvolatile memory cells to the cache memory.

3. 发明授权

US10809925B2 Configurable security memory region 有权
公开(公告)号：US10809925B2
公开(公告)日：2020-10-20
申请号：US16259268
申请日：2019-01-28
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Ken-Hui Chen , Kuen-Long Chang , Chin-Hung Chang , Yu-Chen Wang
IPC分类号： G06F3/06 , G06F12/14
摘要： A memory device comprises a memory array with I/O path and security circuitry coupled to the I/O path of the memory array. The memory device comprises control circuitry, responsive to configuration data, to invoke the security circuitry. The memory device comprises a configuration store, storing the configuration data accessible by the control circuitry to specify location and size of a security memory region in the memory array. Responsive to an external command and the configuration data, the control circuitry can be configured to invoke the security circuitry on an operation specified in the external command in response to accesses into the security memory region, or to not invoke the security circuitry in response to accesses to outside the security memory region.

4. 发明申请

US20200057575A1 Multi-chip package, controlling method of multi-chip package and security chip 审中-公开
公开(公告)号：US20200057575A1
公开(公告)日：2020-02-20
申请号：US15998456
申请日：2018-08-15
申请人： Macronix International Co., Ltd.
发明人： Chia-Jung Chen , Chin-Hung Chang , Ken-Hui Chen
IPC分类号： G06F3/06
摘要： A multi-chip package, a controlling method of the multi-chip package and a security chip are provided. The multi-chip package includes a memory chip and a security chip. The security chip is coupled between the memory chip and a host. The security chip includes a processing circuit. The processing circuit is for enabling a security path to input an input-output signal into the processing circuit for executing a security procedure and accessing the memory chip, if a command is received by the processing circuit and the command includes a security requirement.

5. 发明授权

US10289596B2 Memory and method for operating a memory with interruptible command sequence 有权
公开(公告)号：US10289596B2
公开(公告)日：2019-05-14
申请号：US15411731
申请日：2017-01-20
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Ken-Hui Chen , Kuen-Long Chang , Su-Chueh Lo , Chun-Yu Liao
IPC分类号： G06F13/42 , G06F13/16
摘要： A memory device includes command logic allowing for a command protocol allowing interruption of a first command sequence, such as a page write sequence, and then to proceed directly to receive and decode a second command sequence, such as a read sequence, without latency associated, completing the first command sequence. Also, the command logic is configured to be responsive to a third command sequence after the second command sequence and its associated embedded operation have been completed, which completes the interrupted first command sequence and enables execution of an embedded operation identified by the first command sequence. A memory controller supporting such protocols is described.

6. 发明授权

US10095617B2 Memory device with flexible data transfer rate interface and method thereof 有权
公开(公告)号：US10095617B2
公开(公告)日：2018-10-09
申请号：US14860744
申请日：2015-09-22
申请人： Macronix International Co., Ltd.
发明人： Kuen-Long Chang , Su-Chuch Lo , Chao Hsin Lin , Ken-Hui Chen
IPC分类号： G06F12/06
摘要： A memory device includes an input/output interface configured to receive and output signals. The input/output interface is configured to receive a memory address to be accessed and data sequence information within a clock cycle or at a rising or falling edge of a clock cycle. The data sequence information specifies an input or output data sequence.

7. 发明申请

US20170308463A1 NESTED WRAP-AROUND MEMORY ACCESS 审中-公开
公开(公告)号：US20170308463A1
公开(公告)日：2017-10-26
申请号：US15139252
申请日：2016-04-26
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Kuen-Long Chang , Ken-Hui Chen , Chin-Hung Chang
IPC分类号： G06F12/06
CPC分类号： G06F12/0623 , G06F12/0246 , G06F2212/1044 , G06F2212/2022 , G11C16/08
摘要： A nested wrap-around technology includes an address counter and associated logic for generating addresses to perform a nested wrap-around access operation. The nested wrap-around access operation may be a read or a write operation. A wrap-around section length and a wrap-around count define a wrap-around block. A wrap starting address, initially set to a supplied start address, is offset from a lower boundary of a wrap-around section. Access starts at a wrap starting address and proceeds in a wrap-around manner within a wrap-around section. After access of the address immediately preceding the wrap starting address, the wrap starting address is incremented by the wrap-around section length, or, if the wrap-around section is the last one in the wrap-around block, the wrap starting address is set to the lower boundary of the wrap-around block plus the offset. Access continues until a termination event.

8. 发明授权

US09760434B2 ECC method for double pattern flash memory 有权
公开(公告)号：US09760434B2
公开(公告)日：2017-09-12
申请号：US14841950
申请日：2015-09-01
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Shih-Chang Huang , Ken-Hui Chen , Chun-Hsiung Hung
IPC分类号： G06F11/10 , G11C29/52 , G11C29/04
CPC分类号： G06F11/1068 , G06F11/1052 , G11C29/52 , G11C2029/0411
摘要： A method of operating a memory device storing ECCs for corresponding data is provided. The method includes writing an extended ECC during a first program operation, the extended ECC including an ECC and an extended bit derived from the ECC. The method includes overwriting the extended ECC with a pre-determined state during a second program operation to indicate the second program operation. The method includes, setting the ECC to an initial ECC state before the first program operation; during the first program operation, computing the ECC, changing the ECC to the initial ECC state if the computed ECC equals the pre-determined state; and changing the extended bit to an initial value if the ECC equals the initial ECC state. The method includes reading an extended ECC including an extended bit and an ECC for corresponding data, and determining whether to enable ECC logic using the extended ECC.

9. 发明申请

US20160292031A1 MEMORY DEVICE AND ERASING METHOD THEREOF 有权
公开(公告)号：US20160292031A1
公开(公告)日：2016-10-06
申请号：US15185066
申请日：2016-06-17
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Chin-Hung Chang , Chia-Feng Cheng , Yu-Chen Wang , Ken-Hui Chen , Kuen-Long Chang
IPC分类号： G06F11/10 , G11C11/56 , G11C16/14
CPC分类号： G06F11/1044 , G06F11/1068 , G06F11/1076 , G06F2212/403 , G11C11/5635 , G11C16/00 , G11C16/14 , G11C16/16 , G11C16/3404 , G11C29/42
摘要： An erasing method of a memory device is provided. The memory device includes a memory controller and a memory array having a first memory region and a second memory region. The first memory region and the second memory region share the same well. The erasing method comprising steps of: erasing the first memory region; and selectively programming the second memory region according to an error correction code algorithm.

10. 发明授权

US09450577B1 Circuit with output switch 有权
标题翻译：电路带输出开关
公开(公告)号：US09450577B1
公开(公告)日：2016-09-20
申请号：US14742160
申请日：2015-06-17
申请人： Macronix International Co., Ltd.
发明人： Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Su-Chueh Lo , Tzu-Ting Chiu
IPC分类号： H03K3/00 , H03K17/16
CPC分类号： H03K19/018507
摘要： An output circuit includes: an output switch including a gate terminal, a drain terminal coupled to an external I/O bus, and a well terminal; a well control circuit, having a well terminal coupled to the well terminal of the output switch, to maintain a well voltage of the output switch at a level not less than a greater of a first voltage and a second voltage; and a gate control circuit coupled to the gate terminal and a the drain terminal of the output switch and to the external I/O bus, and operable to turn off the output switch, to prevent current flow through the output switch from the external I/O bus when an operating voltage of the output circuit is not applied to the output switch, and a bus voltage from an external device is present on the external I/O bus.
摘要翻译：输出电路包括：输出开关，包括栅极端子，耦合到外部I / O总线的漏极端子和阱端子; 阱控制电路，具有耦合到输出开关的阱端子的阱端子，以将输出开关的阱电压保持在不小于第一电压和第二电压的较大值的水平; 以及栅极控制电路，其耦合到输出开关的栅极端子和漏极端子和外部I / O总线，并且可操作以关闭输出开关，以防止电流从外部I / O总线流过输出开关， O总线时，输出电路的工作电压不被施加到输出开关，并且来自外部设备的总线电压存在于外部I / O总线上。

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