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1. 发明申请

US20150280761A1 MULTI-LANE SERIAL LINK SIGNAL RECEIVING SYSTEM 有权
标题翻译：多线串行信号接收系统
公开(公告)号：US20150280761A1
公开(公告)日：2015-10-01
申请号：US14670499
申请日：2015-03-27
申请人： MStar Semiconductor, Inc.
发明人： Po-Nien Lin , Meng-Tse Weng , Jiunn-Yih Lee
IPC分类号： H04B1/16 , H04L7/033
CPC分类号： H04L7/033 , H03L7/0807 , H03L7/081 , H04L7/0337
摘要： A multi-lane serial link signal receiving system includes a clock generating circuit and a plurality of data receiving channels. The clock generating circuit provides a fundamental clock signal. Each of the data receiving channels receives an input signal and the fundamental clock signal, and includes a phase detecting circuit, a multi-order digital clock data recovery circuit and a phase adjusting circuit. The phase detecting circuit samples the input signal according to a sampling clock signal to generate a sampled signal. The multi-order digital clock data recovery circuit performs a digital clock data recovery process on the sampled signal to generate phase adjusting information. The phase adjusting circuit adjusts the phase of the fundamental clock signal according to the phase adjusting information to generate the sampling clock signal.
摘要翻译：多通道串行链路信号接收系统包括时钟发生电路和多个数据接收通道。时钟发生电路提供基本时钟信号。每个数据接收通道接收输入信号和基本时钟信号，并且包括相位检测电路，多阶数字时钟数据恢复电路和相位调整电路。相位检测电路根据采样时钟信号对输入信号进行采样，以产生采样信号。多阶数字时钟数据恢复电路对采样信号执行数字时钟数据恢复处理，以产生相位调整信息。相位调整电路根据相位调整信息调整基频时钟信号的相位，生成采样时钟信号。

2. 发明授权

US09276592B2 Multimedia interface receiving circuit 有权
标题翻译：多媒体接口接收电路
公开(公告)号：US09276592B2
公开(公告)日：2016-03-01
申请号：US14582318
申请日：2014-12-24
申请人： MStar Semiconductor, Inc.
发明人： Po-Nien Lin , Jiunn-Yih Lee
IPC分类号： H04B1/10 , H03L7/085 , G09G5/00 , H04L7/033 , H04L7/00
CPC分类号： H03L7/085 , G09G5/006 , G09G5/008 , G09G2370/10 , G09G2370/12 , H03L7/07 , H03L7/0807 , H03L7/081 , H03L7/087 , H04L7/0004 , H04L7/0008 , H04L7/033
摘要： A multimedia interface receiving circuit includes a phase-locked loop (PLL) and four signal processing channels. Each of the channels includes a phase detecting circuit. In a High-Definition Multimedia Interface (HDMI) configuration, one of the processing channels is disabled, and the PLL provides a locked clock signal to the other three processing channels. Each of the other three processing channels adjusts the phase of the locked clock signal to generate a sampling clock signal. In a DisplayPort (DP) configuration, the PLL changes to connect to the phase detecting circuit of one of the four signal processing channels to form an analog clock data recovery (ACDR) circuit to generate a fundamental clock signal. Each of the three other processing channels adjusts the phase of the fundamental clock signal to generate the sampling clock signal.
摘要翻译：多媒体接口接收电路包括锁相环（PLL）和四个信号处理信道。每个通道包括相位检测电路。在高分辨率多媒体接口（HDMI）配置中，处理通道之一被禁用，并且PLL向另外三个处理通道提供锁定的时钟信号。其他三个处理通道中的每一个调节锁定时钟信号的相位以产生采样时钟信号。在DisplayPort（DP）配置中，PLL改变以连接到四个信号处理通道之一的相位检测电路，以形成模拟时钟数据恢复（ACDR）电路，以产生基本时钟信号。三个其他处理通道中的每一个调节基本时钟信号的相位以产生采样时钟信号。

3. 发明授权

US09166847B2 Signal receiving apparatus and two-stage adaptive equalization method thereof 有权
标题翻译：信号接收装置及其两级自适应均衡方法
公开(公告)号：US09166847B2
公开(公告)日：2015-10-20
申请号：US14597391
申请日：2015-01-15
申请人： MStar Semiconductor, Inc.
发明人： Po-Nien Lin , Jyun-Yang Shih , Jiunn-Yih Lee
IPC分类号： H04L27/01 , H04L7/027
CPC分类号： H04L27/01 , H04L7/027 , H04L25/03006 , H04L2025/037
摘要： A signal receiving apparatus includes an equalization module, a coarse tuning module and a fine tuning module. The equalization module receives an input signal, and performs an equalization process on the input signal according to an equalization strength to generate an equalized signal. The coarse tuning module adjusts the equalization strength according to the equalized signal until the equalized signal satisfies a preliminary convergence condition. When the preliminary convergence condition is satisfied, the fine tuning module adjusts the equalization strength according to the equalized signal until the equalization strength satisfies a final convergence condition.
摘要翻译：信号接收装置包括均衡模块，粗调模块和微调模块。均衡模块接收输入信号，根据均衡强度对输入信号进行均衡处理，生成均衡信号。粗调模块根据均衡信号调整均衡强度，直到均衡信号满足预收敛条件。当满足预收敛条件时，微调模块根据均衡信号调整均衡强度，直到均衡强度满足最终的收敛条件。

4. 发明授权

US09419786B2 Multi-lane serial link signal receiving system 有权
标题翻译：多通道串行链路信号接收系统
公开(公告)号：US09419786B2
公开(公告)日：2016-08-16
申请号：US14670499
申请日：2015-03-27
申请人： MStar Semiconductor, Inc.
发明人： Po-Nien Lin , Meng-Tse Weng , Jiunn-Yih Lee
IPC分类号： H04L7/033 , H03L7/08 , H03L7/081
CPC分类号： H04L7/033 , H03L7/0807 , H03L7/081 , H04L7/0337
摘要： A multi-lane serial link signal receiving system includes a clock generating circuit and a plurality of data receiving channels. The clock generating circuit provides a fundamental clock signal. Each of the data receiving channels receives an input signal and the fundamental clock signal, and includes a phase detecting circuit, a multi-order digital clock data recovery circuit and a phase adjusting circuit. The phase detecting circuit samples the input signal according to a sampling clock signal to generate a sampled signal. The multi-order digital clock data recovery circuit performs a digital clock data recovery process on the sampled signal to generate phase adjusting information. The phase adjusting circuit adjusts the phase of the fundamental clock signal according to the phase adjusting information to generate the sampling clock signal.
摘要翻译：多通道串行链路信号接收系统包括时钟发生电路和多个数据接收通道。时钟发生电路提供基本时钟信号。每个数据接收通道接收输入信号和基本时钟信号，并且包括相位检测电路，多阶数字时钟数据恢复电路和相位调整电路。相位检测电路根据采样时钟信号对输入信号进行采样，以产生采样信号。多阶数字时钟数据恢复电路对采样信号执行数字时钟数据恢复处理，以产生相位调整信息。相位调整电路根据相位调整信息调整基频时钟信号的相位，生成采样时钟信号。

5. 发明申请

US20150207652A1 SIGNAL RECEIVING APPARATUS AND TWO-STAGE ADAPTIVE EQUALIZATION METHOD THEREOF 有权
标题翻译：信号接收装置及其两阶段自适应均衡方法
公开(公告)号：US20150207652A1
公开(公告)日：2015-07-23
申请号：US14597391
申请日：2015-01-15
申请人： MStar Semiconductor, Inc.
发明人： Po-Nien Lin , Jyun-Yang Shih , Jiunn-Yih Lee
IPC分类号： H04L27/01 , H04L7/027
CPC分类号： H04L27/01 , H04L7/027 , H04L25/03006 , H04L2025/037
摘要： A signal receiving apparatus includes an equalization module, a coarse tuning module and a fine tuning module. The equalization module receives an input signal, and performs an equalization process on the input signal according to an equalization strength to generate an equalized signal. The coarse tuning module adjusts the equalization strength according to the equalized signal until the equalized signal satisfies a preliminary convergence condition. When the preliminary convergence condition is satisfied, the fine tuning module adjusts the equalization strength according to the equalized signal until the equalization strength satisfies a final convergence condition.
摘要翻译：信号接收装置包括均衡模块，粗调模块和微调模块。均衡模块接收输入信号，根据均衡强度对输入信号进行均衡处理，生成均衡信号。粗调模块根据均衡信号调整均衡强度，直到均衡信号满足预收敛条件。当满足预收敛条件时，微调模块根据均衡信号调整均衡强度，直到均衡强度满足最终的收敛条件。

6. 发明申请

US20150188697A1 MULTIMEDIA INTERFACE RECEIVING CIRCUIT 有权
标题翻译：多媒体接口接收电路
公开(公告)号：US20150188697A1
公开(公告)日：2015-07-02
申请号：US14582318
申请日：2014-12-24
申请人： MStar Semiconductor, Inc.
发明人： Po-Nien Lin , Jiunn-Yih Lee
IPC分类号： H04L7/033 , H03L7/085 , H04L7/00
CPC分类号： H03L7/085 , G09G5/006 , G09G5/008 , G09G2370/10 , G09G2370/12 , H03L7/07 , H03L7/0807 , H03L7/081 , H03L7/087 , H04L7/0004 , H04L7/0008 , H04L7/033
摘要： A multimedia interface receiving circuit includes a phase-locked loop (PLL) and four signal processing channels. Each of the channels includes a phase detecting circuit. In a High-Definition Multimedia Interface (HDMI) configuration, one of the processing channels is disabled, and the PLL provides a locked clock signal to the other three processing channels. Each of the other three processing channels adjusts the phase of the locked clock signal to generate a sampling clock signal. In a DisplayPort (DP) configuration, the PLL changes to connect to the phase detecting circuit of one of the four signal processing channels to form an analog clock data recovery (ACDR) circuit to generate a fundamental clock signal. Each of the three other processing channels adjusts the phase of the fundamental clock signal to generate the sampling clock signal.
摘要翻译：多媒体接口接收电路包括锁相环（PLL）和四个信号处理信道。每个通道包括相位检测电路。在高分辨率多媒体接口（HDMI）配置中，处理通道之一被禁用，并且PLL向另外三个处理通道提供锁定的时钟信号。其他三个处理通道中的每一个调节锁定时钟信号的相位以产生采样时钟信号。在DisplayPort（DP）配置中，PLL改变以连接到四个信号处理通道之一的相位检测电路，以形成模拟时钟数据恢复（ACDR）电路，以产生基本时钟信号。三个其他处理通道中的每一个调节基本时钟信号的相位以产生采样时钟信号。

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