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1. 发明授权

US08719665B2 Programming error correction code into a solid state memory device with varying bits per cell 有权
标题翻译：将错误纠正码编程成固态存储器件，每个单元具有不同位数
公开(公告)号：US08719665B2
公开(公告)日：2014-05-06
申请号：US14056031
申请日：2013-10-17
申请人： Micron Technology, Inc.
发明人： Frankie F. Roohparvar , Vishal Sarin , Jung S. Hoei
IPC分类号： G11C29/00 , H03M13/00 , G06F11/00 , G11C5/14
CPC分类号： G06F11/1076 , G06F11/1072 , G11C29/12005
摘要： Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.
摘要翻译：在特定实施例中，存储设备接收和发送表示两个或多个位的位模式的模拟数据信号，以便于相对于传送指示各个位的数据信号的设备的数据传输速率的增加。编程错误校正码（ECC）和元数据到这种存储器设备中包括基于单元的实际错误率将ECC和元数据存储在每个小区的不同比特级。 ECC和元数据可以与数据块存储在与数据块不同的位级别。如果其中存储数据块的存储器区域不支持在特定位级别的ECC和元数据的期望的可靠性，则ECC和元数据可以以不同的位电平存储在存储器阵列的其他区域中。

2. 发明申请

US20130024736A1 PROGRAMMING ERROR CORRECTION CODE INTO A SOLID STATE MEMORY DEVICE WITH VARYING BITS PER CELL 有权
标题翻译：将错误修正代码编入固态状态存储器件，其中每个单元有不同的位数
公开(公告)号：US20130024736A1
公开(公告)日：2013-01-24
申请号：US13633158
申请日：2012-10-02
申请人： MICRON TECHNOLOGY, INC
发明人： Frankie F. Roohparvar , Vishal Sarin , Jung S. Hoei
IPC分类号： H03M13/05 , G06F11/00 , G11C29/08
CPC分类号： G06F11/1076 , G06F11/1072 , G11C29/12005
摘要： Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.
摘要翻译：在特定实施例中，存储设备接收和发送表示两个或多个位的位模式的模拟数据信号，以便于相对于传送指示各个位的数据信号的设备的数据传输速率的增加。编程错误校正码（ECC）和元数据到这种存储器设备中包括基于单元的实际错误率将ECC和元数据存储在每个小区的不同比特级。 ECC和元数据可以与数据块存储在与数据块不同的位级别。如果其中存储数据块的存储器区域不支持在特定位级别的ECC和元数据的期望的可靠性，则ECC和元数据可以以不同的位电平存储在存储器阵列的其他区域中。

3. 发明授权

US09158612B2 Refresh of non-volatile memory cells based on fatigue conditions 有权
公开(公告)号：US09158612B2
公开(公告)日：2015-10-13
申请号：US14045830
申请日：2013-10-04
申请人： Micron Technology, Inc.
发明人： Frankie F. Roohparvar , Vishal Sarin , Jung S. Hoei
IPC分类号： G11C29/00 , G06F11/07 , G06F11/10 , G11C16/10 , G11C16/34 , G11C29/52 , G11C16/04 , G11C29/04
CPC分类号： G06F11/0751 , G06F11/1068 , G11C16/04 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3431 , G11C16/3495 , G11C29/52 , G11C2029/0409 , G11C2029/0411
摘要： In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block.

4. 发明申请

US20140053033A1 PROGRAMMING ERROR CORRECTION CODE INTO A SOLID STATE MEMORY DEVICE WITH VARYING BITS PER CELL 有权
标题翻译：将错误修正代码编入固态状态存储器件，其中每个单元有不同的位数
公开(公告)号：US20140053033A1
公开(公告)日：2014-02-20
申请号：US14056031
申请日：2013-10-17
申请人： Micron Technology, Inc.
发明人： Frankie F. Roohparvar , Vishal Sarin , Jung S. Hoei
IPC分类号： G06F11/10 , G11C29/12
CPC分类号： G06F11/1076 , G06F11/1072 , G11C29/12005
摘要： Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.
摘要翻译：在特定实施例中，存储设备接收和发送表示两个或多个位的位模式的模拟数据信号，以便于相对于传送指示各个位的数据信号的设备的数据传输速率的增加。编程错误校正码（ECC）和元数据到这样的存储器设备中包括基于单元的实际错误率将ECC和元数据存储在每个小区的不同比特级。 ECC和元数据可以与数据块存储在与数据块不同的位级别。如果其中存储数据块的存储器区域不支持在特定位级别的ECC和元数据的期望的可靠性，则ECC和元数据可以以不同的位电平存储在存储器阵列的其他区域中。

5. 发明申请

US20140040683A1 REFRESH OF NON-VOLATILE MEMORY CELLS BASED ON FATIGUE CONDITIONS 有权
标题翻译：基于疲劳条件的非易失性记忆细胞再造
公开(公告)号：US20140040683A1
公开(公告)日：2014-02-06
申请号：US14045830
申请日：2013-10-04
申请人： Micron Technology, Inc.
发明人： Frankie F. Roohparvar , Vishal Sarin , Jung S. Hoei
IPC分类号： G06F11/07
CPC分类号： G06F11/0751 , G06F11/1068 , G11C16/04 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3431 , G11C16/3495 , G11C29/52 , G11C2029/0409 , G11C2029/0411
摘要： In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block.
摘要翻译：在一个或多个所公开的实施例中，存储器装置中的存储器单元在疲劳状况的指示时被刷新。在一个这样的实施例中，控制器监视单元的行为参数，并且确定是否有任何参数在每个参数设置的正常范围之外，从而指示疲劳状况。如果任何细胞表示疲劳状况，来自指示疲劳的细胞块的数据被移动到另一个块。在一个实施例中，在写入另一个存储块之前对数据执行错误检测和校正处理。

6. 发明授权

US08578244B2 Programming error correction code into a solid state memory device with varying bits per cell 有权
标题翻译：将错误纠正码编程成固态存储器件，每个单元具有不同位数
公开(公告)号：US08578244B2
公开(公告)日：2013-11-05
申请号：US13633158
申请日：2012-10-02
申请人： Micron Technology, Inc
发明人： Frankie F. Roohparvar , Vishal Sarin , Jung S. Hoei
IPC分类号： G11C29/00 , G11C5/14 , H03M13/00 , G06F11/00
CPC分类号： G06F11/1076 , G06F11/1072 , G11C29/12005
摘要： Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.
摘要翻译：在特定实施例中，存储设备接收和发送表示两个或多个位的位模式的模拟数据信号，以便于相对于传送指示各个位的数据信号的设备的数据传输速率的增加。编程错误校正码（ECC）和元数据到这种存储器设备中包括基于单元的实际错误率将ECC和元数据存储在每个小区的不同比特级。 ECC和元数据可以与数据块存储在与数据块不同的位级别。如果其中存储数据块的存储器区域不支持在特定位级别的ECC和元数据的期望的可靠性，则ECC和元数据可以以不同的位电平存储在存储器阵列的其他区域中。

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