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1. 发明授权

US10776362B2 Memory devices for pattern matching 有权
公开(公告)号：US10776362B2
公开(公告)日：2020-09-15
申请号：US16113055
申请日：2018-08-27
申请人： MICRON TECHNOLOGY, INC.
发明人： Luca De Santis , Giulio G. Marotta , Marco-Domenico Tiburzi , Tommaso Vali , Frankie F. Roohparvar , Agostino Macerola
IPC分类号： G06F3/06 , G06F16/2455 , G11C16/06 , G11C7/10 , G11C15/04 , G11C16/04 , G06F7/20 , G06F12/0802 , G11C29/50
摘要： Memory devices for facilitating pattern matching and having an array of memory cells, a plurality of key registers to store a representation of a key word, and a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit from a key register of the plurality of key registers to compare to data stored in the array of memory cells.

2. 发明授权

US10712960B2 Configurable operating mode memory device and methods of operation 有权
公开(公告)号：US10712960B2
公开(公告)日：2020-07-14
申请号：US16166231
申请日：2018-10-22
申请人： MICRON TECHNOLOGY, INC.
发明人： Frankie F. Roohparvar , Luca De Santis , Tommaso Vali , Kenneth J. Eldredge
IPC分类号： G06F3/06 , G11C11/00 , G11C15/04 , G06F11/22 , G06F11/10 , G11C16/04
摘要： Memory devices, and methods of operating similar memory devices, include an array of memory cells comprising a plurality of access lines each configured for biasing control gates of a respective plurality of memory cells of the array of memory cells, wherein the respective plurality of memory cells for one access line of the plurality of access lines is mutually exclusive from the respective plurality of memory cells for each remaining access line of the plurality of access lines, and a controller having a plurality of selectively-enabled operating modes and configured to selectively operate the memory device using two or more concurrently enabled operating modes of the plurality of selectively-enabled operating modes for access of the array of memory cells, with each of the enabled operating modes of the two of more concurrently enabled operating modes utilizing an assigned respective portion of the array of memory cells.

3. 发明申请

US20190341115A1 MEMORY CONFIGURED TO GENERATE A DATA VALUE FROM A DATA LINE CONNECTED TO MORE THAN ONE STRING OF SERIES-CONNECTED MEMORY CELLS 审中-公开
公开(公告)号：US20190341115A1
公开(公告)日：2019-11-07
申请号：US16515134
申请日：2019-07-18
申请人： MICRON TECHNOLOGY, INC.
发明人： Tommaso Vali , Kenneth J. Eldredge , Frankie F. Roohparvar , Luca De Santis
IPC分类号： G11C16/26 , G11C16/08 , G11C7/10 , G06N3/04 , G06N3/063 , G11C16/04
摘要： Memory having an array of memory cells and a controller for access of the array of memory cells that is configured to generate a data value indicative of a level of a property sensed from a data line while applying potentials to control gates of memory cells of more than one string of series-connected memory cells connected to that data line.

4. 发明授权

US10261713B2 Configurable operating mode memory device and methods of operation 有权
公开(公告)号：US10261713B2
公开(公告)日：2019-04-16
申请号：US15945316
申请日：2018-04-04
申请人： MICRON TECHNOLOGY, INC.
发明人： Frankie F. Roohparvar , Luca De Santis , Tommaso Vali , Kenneth J. Eldredge
IPC分类号： G06F3/06 , G11C11/00 , G11C15/04 , G06F11/22 , G06F11/10 , G11C16/04
摘要： Memory devices, and methods of operating similar memory devices, include an array of memory cells comprising a plurality of access lines each configured for biasing control gates of a respective plurality of memory cells of the array of memory cells, wherein the respective plurality of memory cells for one access line of the plurality of access lines is mutually exclusive from the respective plurality of memory cells for each remaining access line of the plurality of access lines, and a controller having a plurality of selectively-enabled operating modes and configured to selectively operate the memory device using two or more concurrently enabled operating modes of the plurality of selectively-enabled operating modes for access of the array of memory cells, with each of the enabled operating modes of the two of more concurrently enabled operating modes utilizing an assigned respective portion of the array of memory cells.

5. 发明授权

US10068653B2 Methods of operating memory 有权
公开(公告)号：US10068653B2
公开(公告)日：2018-09-04
申请号：US15241496
申请日：2016-08-19
申请人： MICRON TECHNOLOGY, INC.
发明人： Tommaso Vali , Kenneth J. Eldredge , Frankie F. Roohparvar , Luca De Santis
IPC分类号： G11C16/10 , G11C16/26 , G06N3/04 , G06N3/063 , G11C16/04 , G11C7/10 , G11C16/08
摘要： Methods of operating memory include generating a data value indicative of a level of a property sensed from a data line while applying potentials to control gates of memory cells of more than one string of series-connected memory cells connected to that data line. Methods of operating memory further include generating data values indicative of levels of a property sensed from data lines while applying potentials to control gates of memory cells of strings of series-connected memory cells connected to those data lines, performing a logical operation on a set of data values comprising those data values, and determining a potential to be applied to control gates of different memory cells of those strings of series-connected memory cells in response to an output of the logical operation on the set of data values.

6. 发明授权

US09548120B2 Content addressable memory 有权
标题翻译：内容可寻址内存
公开(公告)号：US09548120B2
公开(公告)日：2017-01-17
申请号：US14486276
申请日：2014-09-15
申请人： MICRON TECHNOLOGY, INC.
发明人： Frankie F. Roohparvar
IPC分类号： G11C15/00 , G11C15/04 , G11C16/04 , G11C16/08
CPC分类号： G11C15/046 , G11C16/0483 , G11C16/08
摘要： Content addressable memory (CAM) devices provide for high density, low cost CAM devices. CAM devices include a non-volatile memory array having a plurality of NAND memory cell strings, wherein a NAND memory cell string of the non-volatile memory array comprises a plurality of CAM memory cells, and wherein the CAM memory cells comprise non-volatile memory cells of a same NAND memory cell string. The CAM devices further include a control circuit, wherein the control circuit is adapted to search data words stored in the plurality of NAND memory cell strings for a match to at least a portion of an input data word.
摘要翻译：内容可寻址存储器（CAM）器件提供高密度，低成本的CAM器件。 CAM设备包括具有多个NAND存储器单元串的非易失性存储器阵列，其中非易失性存储器阵列的NAND存储器单元串包括多个CAM存储器单元，并且其中CAM存储器单元包括非易失性存储器相同的NAND存储器单元串的单元。 CAM设备还包括控制电路，其中控制电路适于搜索存储在多个NAND存储器单元串中的数据字，以匹配输入数据字的至少一部分。

7. 发明申请

US20160232978A1 MEMORY AS A PROGRAMMABLE LOGIC DEVICE 有权
标题翻译：作为可编程逻辑器件的存储器
公开(公告)号：US20160232978A1
公开(公告)日：2016-08-11
申请号：US15132455
申请日：2016-04-19
申请人： MICRON TECHNOLOGY, INC.
发明人： Luca De Santis , Tommaso Vali , Kenneth J. Eldredge , Frankie F. Roohparvar
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/26 , G11C16/3418
摘要： Methods for operating memory cells include applying a respective minterm, comprising a plurality of variables, to control gates of series strings of memory cells, each series string programmed as a plurality of pairs of complementary memory cells such that certain ones of the plurality of variables are enabled, and logically combining each of the minterms into a logic function output. Memories include a plurality of memory cells configured in series strings of memory cells, wherein each series string of memory cells is configured to provide a minterm comprising a plurality of variables, each variable enabled responsive to a state of an associated, respective memory cell.
摘要翻译：用于操作存储器单元的方法包括应用包括多个变量的相应最小值来控制存储器单元的串联串的栅极，每个串行串被编程为多对互补存储器单元，使得多个变量中的某些变量是启用并逻辑地将每个minterms组合成逻辑功能输出。存储器包括配置成串联的存储器单元串的多个存储器单元，其中存储器单元的每个串联串被配置为提供包括多个变量的最小值，每个变量响应于相关联的相应存储单元的状态而启用。

8. 发明授权

US09105330B1 Memory devices configured to apply different weights to different strings of memory cells coupled to a data line and methods 有权
标题翻译：配置为将不同的权重应用于耦合到数据线和方法的不同存储器单元串的存储器件
公开(公告)号：US09105330B1
公开(公告)日：2015-08-11
申请号：US13864659
申请日：2013-04-17
申请人： Micron Technology, Inc.
发明人： Kenneth J. Eldredge , Frankie F. Roohparvar , Luca de Santis , Tommaso Vali
IPC分类号： G11C15/00
CPC分类号： G11C16/28 , G11C15/00 , G11C15/046 , G11C16/0483
摘要： Memory devices and methods are disclosed. One such method compares input data to stored data in a memory device and includes applying a first weight factor to a first string of memory cells coupled to a data line, where a first bit of the stored data is stored in the first string of memory cells; applying a second weight factor to a second string of memory cells coupled to the data line, where a second bit of the stored data is stored in the second string of memory cells; comparing a first bit of input data to the first bit of the stored data while the first weight factor is applied to the first string of memory cells; and comparing a second bit of the input data to the second bit of the stored data while the second weight factor is applied to the second string of memory cells.
摘要翻译：公开了存储器件和方法。一种这样的方法将输入数据与存储器件中的存储数据进行比较，并且包括将第一加权因子应用于耦合到数据线的存储器单元的第一串，其中存储的数据的第一位被存储在第一存储单元串中 ; 将第二加权因子应用于耦合到所述数据线的第二存储单元串，其中所述存储数据的第二位存储在所述第二存储单元串中; 将第一加权因子应用于第一串存储器单元时，将第一比特的输入数据与存储数据的第一比较; 以及将所述输入数据的第二位与存储的数据的第二位进行比较，同时将所述第二权重因子应用于所述第二存储单元串。

9. 发明授权

US08719665B2 Programming error correction code into a solid state memory device with varying bits per cell 有权
标题翻译：将错误纠正码编程成固态存储器件，每个单元具有不同位数
公开(公告)号：US08719665B2
公开(公告)日：2014-05-06
申请号：US14056031
申请日：2013-10-17
申请人： Micron Technology, Inc.
发明人： Frankie F. Roohparvar , Vishal Sarin , Jung S. Hoei
IPC分类号： G11C29/00 , H03M13/00 , G06F11/00 , G11C5/14
CPC分类号： G06F11/1076 , G06F11/1072 , G11C29/12005
摘要： Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.
摘要翻译：在特定实施例中，存储设备接收和发送表示两个或多个位的位模式的模拟数据信号，以便于相对于传送指示各个位的数据信号的设备的数据传输速率的增加。编程错误校正码（ECC）和元数据到这种存储器设备中包括基于单元的实际错误率将ECC和元数据存储在每个小区的不同比特级。 ECC和元数据可以与数据块存储在与数据块不同的位级别。如果其中存储数据块的存储器区域不支持在特定位级别的ECC和元数据的期望的可靠性，则ECC和元数据可以以不同的位电平存储在存储器阵列的其他区域中。

10. 发明授权

US08693246B2 Memory controller self-calibration for removing systemic influence 有权
标题翻译：内存控制器自校准，用于消除系统影响
公开(公告)号：US08693246B2
公开(公告)日：2014-04-08
申请号：US13749850
申请日：2013-01-25
申请人： Micron Technology, Inc.
发明人： Frankie F. Roohparvar , Vishal Sarin , Jung-Sheng Hoei
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10 , G11C16/04 , G11C16/20 , G11C29/028 , G11C29/12005 , G11C29/50 , G11C29/50004 , G11C2029/5004
摘要： Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming operations, the voltage on the selected cell is read to determine any change in voltage caused by systemic offsets such as, for example, floating gate-to-floating gate coupling. These changes are averaged and stored in a table as an offset for use in adjusting a programming voltage or a read voltage in a particular area of memory represented by the offset. Self calibration method for temperature is determined by writing cells at different temperatures and reading at different temperatures to generate temperature offset tables for the write path and read path. These offset tables are used to adjust for systematic temperature related offsets during programming and during read.
摘要翻译：通过向所选择的单元写入电压来执行存储器控制器的自校准。对所选单元格周围的相邻单元进行编程。在每个相邻的编程操作之后，读取所选择的单元上的电压，以确定由例如浮动栅极到浮置栅极耦合的系统偏移引起的任何电压变化。这些变化被平均并存储在表中作为用于调整由偏移表示的存储器的特定区域中的编程电压或读取电压的偏移。通过在不同温度下写入单元格并在不同温度读取来确定温度的自校准方法，以生成写入路径和读取路径的温度偏移表。这些偏移表用于在编程期间和读取期间调整与系统温度相关的偏移。

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