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1. 发明授权

US06245595B1 Techniques for wafer level molding of underfill encapsulant 有权
标题翻译：底层填料密封剂晶圆级成型技术
公开(公告)号：US06245595B1
公开(公告)日：2001-06-12
申请号：US09359074
申请日：1999-07-22
申请人： Luu Nguyen , Hem P. Takiar , Ethan Warner , Shahram Mostafazadeh , Joseph O. Smith
发明人： Luu Nguyen , Hem P. Takiar , Ethan Warner , Shahram Mostafazadeh , Joseph O. Smith
IPC分类号： H01L2144
CPC分类号： H01L21/67126 , H01L21/563 , H01L24/11 , H01L24/29 , H01L24/94 , H01L2224/05568 , H01L2224/05573 , H01L2224/056 , H01L2224/13099 , H01L2224/16 , H01L2224/274 , H01L2224/73104 , H01L2224/73203 , H01L2224/83191 , H01L2224/83856 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/351 , H01L2924/01031 , H01L2924/3512 , H01L2924/00 , H01L2924/00014
摘要： A method and apparatus for forming a layer of underfill encapsulant on an integrated circuit located on a wafer are described. As a flip chip, the integrated circuit has electrically conductive pads, most of which have a solder ball attached thereto. Most of the solder balls have been flattened in order to provide an enlarged solder wetting area. A layer of underfill encapsulant is injected onto the integrated circuit under pressure to form a layer of underfill encapsulant that is then pre-cured. The integrated circuit is mounted to a substrate and the substrate and the integrated circuit are electrically coupled by a solder reflow operation which also finally cures the underfill encapsulant.
摘要翻译：描述了在位于晶片上的集成电路上形成底层密封剂层的方法和装置。作为倒装芯片，集成电路具有导电焊盘，其中大部分具有附着于其上的焊球。大多数焊球已经被平坦化，以便提供扩大的焊料润湿区域。将一层底层填料密封剂在压力下注入到集成电路上，以形成一层底层填料密封剂，然后将其预固化。集成电路安装到基板上，并且基板和集成电路通过回流焊接操作电耦合，焊接回流操作也最终固化底部填充密封剂。

2. 发明授权

US07144800B2 Multichip packages with exposed dice 有权
标题翻译：带裸露裸片的多芯片封装
公开(公告)号：US07144800B2
公开(公告)日：2006-12-05
申请号：US10890896
申请日：2004-07-13
申请人： Shahram Mostafazadeh , Joseph O. Smith
发明人： Shahram Mostafazadeh , Joseph O. Smith
IPC分类号： H01L21/00 , H01L23/495 , H01L23/02 , H01L29/40
CPC分类号： H01L23/3107 , H01L21/561 , H01L21/563 , H01L21/568 , H01L23/49548 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/94 , H01L24/97 , H01L2223/54493 , H01L2224/16145 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48247 , H01L2224/73253 , H01L2224/73265 , H01L2224/94 , H01L2224/97 , H01L2924/00014 , H01L2924/01027 , H01L2924/01029 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/15311 , H01L2924/15747 , H01L2924/181 , H01L2924/1815 , H01L2924/18161 , H01L2924/18165 , H01L2924/3025 , H01L2224/81 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/05599 , H01L2224/0401
摘要： Multichip packages and methods for making same. The present invention generally allows for either the back of a flipchip, the back of a mother die, or both to be exposed in a multichip package. When the mother die is connected to the package contacts, the back of the flip chip is higher than the electrical connections. Accordingly, the back of the flip chip can be exposed. Furthermore, if a temporary tape substrate is used with a leadframe panel that does not have a die attach pad, the package can be even thinner. Once the temporary tape substrate is removed, both the back of the flipchip and the back of the mother die will be exposed from the encapsulant.
摘要翻译： Multichip包和其制作方法。本发明通常允许倒装芯片的背面，母模的背面或两者都暴露在多芯片封装中。当母体裸片连接到封装触点时，倒装芯片的背面高于电气连接。因此，可以暴露倒装芯片的背面。此外，如果临时带基板与不具有管芯附接垫的引线框面板一起使用，则封装可以更薄。一旦临时的胶带基板被去除，倒装芯片的背面和母模的背面都将从密封剂暴露出来。

3. 发明授权

US06936929B1 Multichip packages with exposed dice 有权
标题翻译：带裸露裸片的多芯片封装
公开(公告)号：US06936929B1
公开(公告)日：2005-08-30
申请号：US10391160
申请日：2003-03-17
申请人： Shahram Mostafazadeh , Joseph O. Smith
发明人： Shahram Mostafazadeh , Joseph O. Smith
IPC分类号： H01L21/56 , H01L23/31 , H01L23/495 , H01L29/40
CPC分类号： H01L23/3107 , H01L21/561 , H01L21/563 , H01L21/568 , H01L23/49548 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/94 , H01L24/97 , H01L2223/54493 , H01L2224/16145 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48247 , H01L2224/73253 , H01L2224/73265 , H01L2224/94 , H01L2224/97 , H01L2924/00014 , H01L2924/01027 , H01L2924/01029 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/15311 , H01L2924/15747 , H01L2924/181 , H01L2924/1815 , H01L2924/18161 , H01L2924/18165 , H01L2924/3025 , H01L2224/81 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/05599 , H01L2224/0401
摘要： Multichip packages and methods for making same. The present invention generally allows for either the back of a flipchip, the back of a mother die, or both to be exposed in a multichip package. When the mother die is connected to the package contacts, the back of the flip chip is higher than the electrical connections. Accordingly, the back of the flip chip can be exposed. Furthermore, if a temporary tape substrate is used with a leadframe panel that does not have a die attach pad, the package can be even thinner. Once the temporary tape substrate is removed, both the back of the flipchip and the back of the mother die will be exposed from the encapsulant.
摘要翻译： Multichip包和其制作方法。本发明通常允许倒装芯片的背面，母模的背面或两者都暴露在多芯片封装中。当母体裸片连接到封装触点时，倒装芯片的背面高于电气连接。因此，可以暴露倒装芯片的背面。此外，如果临时带基板与不具有管芯附接垫的引线框面板一起使用，则封装可以更薄。一旦临时的胶带基板被去除，倒装芯片的背面和母模的背面都将从密封剂暴露出来。

4. 发明授权

US06888228B1 Lead frame chip scale package 有权
标题翻译：引线框架芯片级封装
公开(公告)号：US06888228B1
公开(公告)日：2005-05-03
申请号：US09625071
申请日：2000-07-25
申请人： Shahram Mostafazadeh , Joseph O. Smith
发明人： Shahram Mostafazadeh , Joseph O. Smith
IPC分类号： H01L21/56 , H01L21/68 , H01L23/24 , H01L23/495
CPC分类号： H01L21/568 , H01L21/561 , H01L23/24 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/0101 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/85 , H01L2924/00 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012
摘要： In one aspect of the invention, a lead frame panel suitable for use in packaging an array of integrated circuits is described. The lead frame panel includes a matrix of tie bars that extend in substantially perpendicular rows and columns to define a two dimensional array of immediately adjacent device areas separated only by the tie bars. Each device area is suitable for use in an independent integrated circuit package and includes a die attach pad and a plurality of conductive contacts. In another aspect of the invention, a panel assembly suitable for use in simultaneously packaging a multiplicity of integrated circuits is described. The panel assembly includes a lead frame panel formed from a conductive sheet. The lead frame panel is patterned to define at least one two dimensional array of adjacent device areas. Each device area is suitable for use as part of an independent integrated circuit package and including a die and a plurality of contacts positioned around and electrically connected to the die. A molded cap is also provided that substantially uniformly covers a two dimensional array of adjacent device areas while leaving bottom surfaces of the conductive contacts exposed to facilitate electrical connection to external components. The encapsulation material that forms the molded cap is exposed at a bottom surface of the panel of integrated circuits to physically isolate the contacts.
摘要翻译：在本发明的一个方面，描述了适用于封装集成电路阵列的引线框架面板。引线框架面板包括一系列连接杆，其基本垂直的行和列延伸，以限定仅由连接杆分离的紧邻设备区域的二维阵列。每个器件区域适用于独立的集成电路封装，并且包括管芯附接焊盘和多个导电触点。在本发明的另一方面，描述了适用于同时封装多个集成电路的面板组件。面板组件包括由导电片形成的引线框架面板。图案化引线框架面板以限定相邻设备区域的至少一个二维阵列。每个器件区域适合用作独立集成电路封装的一部分，并且包括管芯和定位在芯片周围并电连接到管芯的多个触点。还提供了模制盖，其基本上均匀地覆盖相邻设备区域的二维阵列，同时使导电触头的底表面暴露以促进与外部组件的电连接。形成模制帽的封装材料暴露在集成电路板的底表面以物理地隔离触点。

5. 发明授权

US06710246B1 Apparatus and method of manufacturing a stackable package for a semiconductor device 有权
标题翻译：制造用于半导体器件的可堆叠封装的装置和方法
公开(公告)号：US06710246B1
公开(公告)日：2004-03-23
申请号：US10211450
申请日：2002-08-02
申请人： Shahram Mostafazadeh , Joseph O. Smith
发明人： Shahram Mostafazadeh , Joseph O. Smith
IPC分类号： H01L2302
CPC分类号： H01L24/97 , H01L21/561 , H01L23/3107 , H01L23/49548 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/105 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/73265 , H01L2224/97 , H01L2225/1029 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01077 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , H01L2924/3011 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： A package, a method of making and a method of assembly of packages for semiconductor chips are disclosed. The package includes a die attach pad on which a semiconductor die is mounted. A lead is electrically connected to the semiconductor die which is encapsulated in packaging material. The lead is exposed at opposed sides of the package. Exposing the lead on both sides of the package allows the package to be stacked or assembled so that the leads of adjacent pairs of packages are in electrical contact. Making the semiconductor packages includes forming a piece of electrically conductive material into a die attach pad and at least one lead associated with the die attach pad. A semiconductor die is mounted on the die attach pad and an electrical connection is made between the semiconductor die and the lead. The package is formed by encapsulation with the lead exposed on opposite sides of the package.
摘要翻译：公开了一种用于半导体芯片的封装，封装方法和组装方法。该封装包括其上安装有半导体管芯的管芯附接焊盘。引线与封装在封装材料中的半导体管芯电连接。引线暴露在封装的相对两侧。在封装的两侧露出引线允许封装被堆叠或组装，使得相邻封装对的引线电接触。制造半导体封装包括将一块导电材料形成到管芯附接焊盘和与管芯附接焊盘相关联的至少一个引线。半导体管芯安装在管芯附接焊盘上，并且在半导体管芯和引线之间形成电连接。封装通过封装形成，引线暴露在封装的相对两侧。

6. 发明授权

US6054772A Chip sized package 失效
标题翻译：芯片尺寸封装
公开(公告)号：US6054772A
公开(公告)日：2000-04-25
申请号：US70111
申请日：1998-04-29
申请人： Shahram Mostafazadeh , Joseph O. Smith
发明人： Shahram Mostafazadeh , Joseph O. Smith
IPC分类号： H01L23/31 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/3107 , H01L2224/1134 , H01L2224/94
摘要： An improved wafer based packaging arrangement for integrated circuits is disclosed. In one aspect of the invention, external contacts are formed for the packaged integrated circuits by contact studs formed from bonding wires. One end of each contact studs is ball bonded to an associated wafer bond pad. An elongated portion of each wire (contact stud) extends outward the wafer surface and terminates at a second end that forms an external contact. Filling material surrounds a significant portion of the contact studs to hold the studs in place but leaves at least a portion of the second ends exposed to form external contacts. In some embodiments, the external contacts are substantially coplanar with the surface of the filling material, while in others, a protrusion beyond the filling material surface is left to form a contact bump. The wafers are eventually diced to form discrete packaged integrated circuits having external contacts formed by the contact studs.
摘要翻译：公开了用于集成电路的改进的基于晶片的封装装置。在本发明的一个方面，通过由接合线形成的接触柱形成用于封装的集成电路的外部接触。每个接触螺柱的一端球焊接到相关联的晶片接合焊盘。每个线（接触柱）的细长部分向外延伸晶片表面，并终止于形成外部接触的第二端。填充材料围绕接触柱的重要部分以将螺柱保持在适当的位置，但是将第二端的至少一部分暴露以形成外部接触。在一些实施例中，外部触点与填充材料的表面基本上共面，而在另一些实施例中，留下超过填充材料表面的突起形成接触凸块。最终切割晶片以形成具有由接触柱形成的外部触头的分立的封装集成电路。

7. 发明授权

US07468288B1 Die-level opto-electronic device and method of making same 有权
标题翻译：晶体级光电器件及其制造方法
公开(公告)号：US07468288B1
公开(公告)日：2008-12-23
申请号：US11481699
申请日：2006-07-05
申请人： Shahram Mostafazadeh , Joseph O. Smith
发明人： Shahram Mostafazadeh , Joseph O. Smith
IPC分类号： H01L21/00 , H01L21/44
CPC分类号： H01L31/0203 , H01L23/481 , H01L24/10 , H01L24/13 , H01L24/48 , H01L24/81 , H01L27/14618 , H01L33/62 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/056 , H01L2224/13 , H01L2224/131 , H01L2224/16237 , H01L2224/48091 , H01L2224/48227 , H01L2224/81801 , H01L2924/00013 , H01L2924/00014 , H01L2924/01006 , H01L2924/01027 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15153 , H01L2924/15165 , H01L2924/16195 , H01L2224/13099 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： The invention includes a die-level opto-electronic device with a semiconductor die and a photonic device including a conductive structure formed in the die away from the edges of the die. The conductive structure is electrically connected to the photonic device. The device also includes an optically transparent laminate attached to overlay the photonic device. The invention also comprises a semiconductor wafer with a plurality of photonic devices exposed on a first surface and a plurality of conductive structures being exposed on a second surface opposing the first surface. The conductive structures are electrically connected to the photonic devices which are overlaid with an optically transparent laminate. The invention further includes methods of forming die-level opto-electronic devices and semiconductor wafers.
摘要翻译：本发明包括具有半导体管芯的管芯级光电器件和包括在模具中形成的导电结构的光子器件，远离管芯的边缘。导电结构电连接到光子器件。该装置还包括附着以覆盖光子装置的光学透明层压体。本发明还包括具有暴露在第一表面上的多个光子器件的半导体晶片，并且在与第一表面相对的第二表面上露出多个导电结构。导电结构电连接到用光学透明层压体覆盖的光子器件。本发明还包括形成管芯级光电器件和半导体晶片的方法。

8. 再颁专利

USRE39854E1 Lead frame chip scale package 有权
标题翻译：引线框架芯片级封装
公开(公告)号：USRE39854E1
公开(公告)日：2007-09-25
申请号：US10260044
申请日：2002-09-27
申请人： Shahram Mostafazadeh , Joseph O. Smith
发明人： Shahram Mostafazadeh , Joseph O. Smith
IPC分类号： H01L23/495
CPC分类号： H01L21/568 , H01L21/561 , H01L23/24 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/0101 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/85 , H01L2924/00 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012
摘要： A method for producing chip scale IC packages includes the step of mounting a lead frame panel on a temporary support fixture in order to provide support and protection during the manufacturing process. An embodiment of the temporary support fixture includes a sheet of sticky tape secured to a rigid frame. The rigid frame maintains tension in the sheet of sticky tape to provide a stable surface to which the lead frame panel can be affixed. Installation of IC chips and encapsulation in protective casings is performed as in conventional IC package manufacturing. If encapsulant material is to be dispensed over the IC chips, an encapsulant dam can be formed around the lead frame panel to contain the flow of encapsulant material. The temporary support fixture can be used in any IC package manufacturing process in which lead frames require supplemental support.
摘要翻译：制造芯片级IC封装的方法包括将引线框架面板安装在临时支撑固定装置上以便在制造过程中提供支撑和保护的步骤。临时支撑固定装置的一个实施例包括固定到刚性框架的粘性片材片。刚性框架保持粘性胶带中的张力，以提供稳定的表面，引线框架面板可以固定到该表面上。 IC芯片的安装和保护套管中的封装按照传统的IC封装制造进行。如果将密封剂材料分配在IC芯片上，则可以在引线框架板周围形成密封剂坝以容纳密封材料的流动。临时支撑夹具可用于任何IC封装制造工艺，其中引线框架需要补充支撑。

9. 发明授权

US07171745B2 Apparatus and method for force mounting semiconductor packages to printed circuit boards 有权
标题翻译：将半导体封装强制安装到印刷电路板的装置和方法
公开(公告)号：US07171745B2
公开(公告)日：2007-02-06
申请号：US10956200
申请日：2004-09-30
申请人： Shahram Mostafazadeh , Joseph O. Smith
发明人： Shahram Mostafazadeh , Joseph O. Smith
IPC分类号： H05K3/30
CPC分类号： H05K3/325 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48227 , H01L2224/73265 , H01L2924/14 , H01L2924/15311 , H05K2201/10121 , H05K2201/10234 , H05K2201/10719 , H05K2201/10734 , Y10T29/4913 , Y10T29/49131 , Y10T29/49144 , Y10T29/49208 , Y10T29/53174 , Y10T29/53178 , Y10T29/53183 , H01L2924/00012 , H01L2924/00
摘要： An apparatus and method for force mounting semiconductor packages onto printed circuit boards without the use of solder. The apparatus includes a substrate, a first integrated circuit die mounted onto the substrate, a housing configured to house the first integrated circuit die mounted onto the substrate, and a force mechanism configured to force mount the housing including the integrated circuit die and substrate onto a printed circuit board. The method includes mounting a first integrated circuit die onto a first surface of a substrate, housing the first integrated circuit die mounted onto the substrate in a housing, and using a force mechanism to force mount the housing including the first integrated circuit die mounted on the substrate onto a printed circuit board. According to various embodiments, the force mechanism includes one of the following types of force mechanisms clamps, screws, bolts, adhesives, epoxy, or Instrument housings or heat stakes.
摘要翻译：一种在不使用焊料的情况下将半导体封装强制安装到印刷电路板上的装置和方法。该装置包括基板，安装在基板上的第一集成电路芯片，被构造成容纳安装在基板上的第一集成电路芯片的壳体，以及强制机构，其被构造成将包括集成电路管芯和基板的壳体安装到印刷电路板。该方法包括将第一集成电路管芯安装到衬底的第一表面上，将安装在衬底上的第一集成电路管芯容纳在壳体中，并且使用力机构来强制安装壳体，该壳体包括安装在衬底上的第一集成电路管芯衬底到印刷电路板上。根据各种实施例，力机构包括以下类型的力机构夹具，螺钉，螺栓，粘合剂，环氧树脂或仪器壳体或热桩中的一种。

10. 发明授权

US06984866B1 Flip chip optical semiconductor on a PCB 有权
标题翻译：在PCB上倒装芯片光学半导体
公开(公告)号：US06984866B1
公开(公告)日：2006-01-10
申请号：US10391283
申请日：2003-03-17
申请人： Shahram Mostafazadeh , Joseph O. Smith , Matthew D. Penry
发明人： Shahram Mostafazadeh , Joseph O. Smith , Matthew D. Penry
IPC分类号： H01L31/0203
CPC分类号： H01L31/0203 , H01L27/14618 , H01L2924/15192
摘要： Semiconductor devices and methods for making semiconductor devices. The present invention allows a flip chip assembly to be used with an optical semiconductor device. The optical semiconductor flip chip is positioned over a hole in a PCB such that the imaging area of the optical semiconductor flip chip faces the hole. The hole allows the imaging area to be unobstructed by the PCB. Underfill material can be prevented from going into the hole by erecting a barrier on top of the PCB that surrounds the hole.
摘要翻译：用于制造半导体器件的半导体器件和方法。本发明允许与光学半导体器件一起使用倒装芯片组件。光学半导体倒装芯片位于PCB中的孔的上方，使得光学半导体倒装芯片的成像区域面向孔。该孔允许成像区域被PCB阻挡。可以通过在围绕孔的PCB的顶部上竖立阻挡层来防止底部填充材料进入孔中。

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