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1. 发明授权

US06577529B1 Multi-bit magnetic memory device 有权
标题翻译：多位磁记忆体装置
公开(公告)号：US06577529B1
公开(公告)日：2003-06-10
申请号：US10235011
申请日：2002-09-03
申请人： Manish Sharma , Thomas C. Anthony , Lung T. Tran
发明人： Manish Sharma , Thomas C. Anthony , Lung T. Tran
IPC分类号： G11C1100
CPC分类号： G11C11/15 , G11C11/5607 , G11C2213/71
摘要： A memory cell includes a conductor clad with ferromagnetic material; first and second spacer layers on opposite sides of the clad conductor; a first data layer on the first spacer layer; and a second data layer on the second spacer layer.
摘要翻译：存储单元包括用铁磁材料包覆的导体; 在包层导体的相对侧上的第一和第二间隔层; 第一间隔层上的第一数据层; 以及第二间隔层上的第二数据层。

2. 发明授权

US06693825B1 Magneto-resistive device including clad conductor 有权
标题翻译：包括包层导体的磁阻装置
公开(公告)号：US06693825B1
公开(公告)日：2004-02-17
申请号：US10349685
申请日：2003-01-23
申请人： Manish Sharma , Thomas C. Anthony , Lung T. Tran
发明人： Manish Sharma , Thomas C. Anthony , Lung T. Tran
IPC分类号： G11C1100
CPC分类号： G11C11/15 , G11C11/5607 , G11C2213/71
摘要： A memory cell includes a conductor clad with ferromagnetic material; first and second spacer layers on opposite sides of the clad conductor; a first data layer on the first spacer layer; and a second data layer on the second spacer layer.
摘要翻译：存储单元包括用铁磁材料包覆的导体; 在包层导体的相对侧上的第一和第二间隔层; 第一间隔层上的第一数据层; 以及第二间隔层上的第二数据层。

3. 发明授权

US06473337B1 Memory device having memory cells with magnetic tunnel junction and tunnel junction in series 失效
标题翻译：具有存储单元的存储器件，其具有磁性隧道结和隧道结
公开(公告)号：US06473337B1
公开(公告)日：2002-10-29
申请号：US09983404
申请日：2001-10-24
申请人： Lung T. Tran , Manish Sharma , Thomas C. Anthony
发明人： Lung T. Tran , Manish Sharma , Thomas C. Anthony
IPC分类号： G11C1115
CPC分类号： H01L27/222 , G11C11/15
摘要： A memory device includes dual tunnel junction memory cells having a magnetic tunnel junction in series with a tunnel junction. The magnetic tunnel junction can be changed from a first resistance state to a second resistance state during a write operation. The magnetic tunnel junction can have a differing resistance-voltage characteristic than the tunnel junction, and the differing resistance-voltage characteristics allow the magnetic tunnel junction to be blown without blowing the tunnel junction during a write operation. The change in resistance state of the magnetic tunnel junction changes the resistance of the selected memory cell, which is detectable during a read operation.
摘要翻译：存储器件包括双隧道结存储器单元，其具有与隧道结串联的磁性隧道结。在写入操作期间，磁性隧道结可以从第一电阻状态改变到第二电阻状态。磁性隧道结可以具有与隧道结不同的电阻 - 电压特性，并且不同的电阻 - 电压特性允许磁性隧道结在写入操作期间不会吹动隧道结而被吹动。磁性隧道结的电阻状态的改变改变了所选择的存储单元的电阻，这在读取操作期间是可检测的。

4. 发明授权

US06961263B2 Memory device with a thermally assisted write 有权
标题翻译：具有热辅助写入的存储器件
公开(公告)号：US06961263B2
公开(公告)日：2005-11-01
申请号：US10657519
申请日：2003-09-08
申请人： Kenneth K. Smith , Thomas C. Anthony , Lung T. Tran
发明人： Kenneth K. Smith , Thomas C. Anthony , Lung T. Tran
IPC分类号： G11C11/15 , G11C11/14 , G11C5/06
CPC分类号： G11C11/15 , G11C11/1675
摘要： A memory device includes an array of magnetic storage cells. Each magnetic storage cell in the array includes a set of conductors used to write data to a storage cell and a second set of conductors used to heat the magnetic storage cell and read data from the magnetic storage cell. The magnetic storage cells can be used in electronic systems such as a computer system or consumer electronic system.
摘要翻译：存储器件包括磁存储单元阵列。阵列中的每个磁存储单元包括用于向存储单元写入数据的一组导体和用于加热磁存储单元并从磁存储单元读取数据的第二组导体。磁存储单元可用于诸如计算机系统或消费电子系统的电子系统中。

5. 发明授权

US5930087A Robust recording head for near-contact operation 失效
标题翻译：坚固的记录头，用于近距离操作
公开(公告)号：US5930087A
公开(公告)日：1999-07-27
申请号：US974420
申请日：1997-11-20
申请人： James A. Brug , Manoj K. Bhattacharyya , Lung T. Tran , Thomas C. Anthony
发明人： James A. Brug , Manoj K. Bhattacharyya , Lung T. Tran , Thomas C. Anthony
IPC分类号： G11B5/11 , G11B5/33 , G11B5/39 , G11B5/40 , G11B19/04 , H01F10/32
CPC分类号： B82Y25/00 , B82Y10/00 , G11B5/33 , G11B5/332 , G11B5/3903 , G11B5/3909 , G11B5/3919 , G11B5/40 , H01F10/3268 , G11B19/04 , G11B5/11 , G11B5/3912 , G11B5/3967
摘要： A robust recording head with a spin tunneling sensing element separated from an interface between the recording head and a recording media so as not to be affected by collisions and other ill effects at the interface between the recording head and the recording media. The spin tunneling sensing element includes a pair of magnetic elements wherein one of the magnetic elements functions as a flux guide that conducts magnetic flux emanating from the recording media away from the interface to an active area of the spin tunneling sensing element.
摘要翻译：一种坚固的记录头，其具有与记录头和记录介质之间的接口分开的自旋隧道感测元件，以便不受记录头和记录介质之间的界面处的碰撞和其它不良影响的影响。自旋隧道感测元件包括一对磁性元件，其中一个磁性元件用作将从记录介质发出的磁通远离界面移动到自旋隧道感应元件的有效区域的磁通引导件。

6. 发明授权

US06727105B1 Method of fabricating an MRAM device including spin dependent tunneling junction memory cells 有权
标题翻译：制造包括自旋相关隧道结存储器单元的MRAM器件的方法
公开(公告)号：US06727105B1
公开(公告)日：2004-04-27
申请号：US09514934
申请日：2000-02-28
申请人： James A. Brug , Lung T. Tran , Thomas C. Anthony , Manoj K. Bhattacharyya , Janice Nickel
发明人： James A. Brug , Lung T. Tran , Thomas C. Anthony , Manoj K. Bhattacharyya , Janice Nickel
IPC分类号： H01L2100
CPC分类号： H01F10/3254 , B82Y10/00 , B82Y25/00 , G11C11/16 , H01L27/222 , H01L43/08
摘要： A spin dependent tunneling (“SDT”) junction of a memory cell for a Magnetic Random Access Memory (“MRAM”) device includes a pinned ferromagnetic layer, followed by an insulating tunnel barrier and a sense ferromagnetic layer. During fabrication of the MRAM device, after formation of the pinned layer but before formation of the insulating tunnel barrier, an exposed surface of the pinned layer is flattened. The exposed surface of the pinned layer may be flattened by an ion etching process.
摘要翻译：用于磁随机存取存储器（“MRAM”）器件的存储器单元的自旋相关隧道（“SDT”）结包括钉扎铁磁层，随后是绝缘隧道势垒和感测铁磁层。在制造MRAM器件期间，在形成钉扎层之后但在形成绝缘隧道势垒之前，被钉扎层的暴露表面变平。被钉扎层的暴露表面可以通过离子蚀刻工艺变平。

7. 发明授权

US06504742B1 3-D memory device for large storage capacity 有权
标题翻译： 3-D存储设备，存储容量大
公开(公告)号：US06504742B1
公开(公告)日：2003-01-07
申请号：US09984934
申请日：2001-10-31
申请人： Lung T. Tran , Thomas C. Anthony
发明人： Lung T. Tran , Thomas C. Anthony
IPC分类号： G11C502
CPC分类号： H01L27/10897 , G11C5/02 , G11C5/025 , G11C8/12 , G11C13/0023 , G11C2213/71 , H01L21/8221 , H01L27/0688 , H01L27/10805 , H01L2924/0002 , H01L2924/00
摘要： A random access memory (memory) includes one or more planes of memory arrays stacked on top of each other. Each plane may be manufactured separately, and each array within the plane may be enabled/disabled separately. In this manner, each memory array within the plane can be individually tested, and defective memory arrays may be sorted out, which increases the final yield and quality. A memory plane may be stacked on top of each other and on top of an active circuit plane to make a large capacity memory device. The memory may be volatile or non-volatile by using appropriate memory cells as base units. Also, the memory plane may be fabricated separately from the active circuitry. Thus the memory plane does not require a silicon substrate, and may be formed from a glass substrate for example. Further, each memory plane may be individually selected (or enabled) via plane memory select transistors. The array may be individually selected (or enable) via array select transistor. These transistors may be formed from amorphous silicon transistor(s) and/or thin-film transistor(s). The data bus, array select bus, and the plane select bus provide electrical connections between the memory planes and the active circuit plane via side contact pads on each plane. 3-D memory for large storage capacity. The memory may be formed from one or more planes with each plane including one or more memory arrays. Each memory array of each plane may be separately enabled or disabled. The memory array may be formed on silicon or non-silicon based substrate. An active circuit plane may be shared among the memory arrays and planes to perform read and write functions.
摘要翻译：随机存取存储器（存储器）包括堆叠在彼此之上的一个或多个存储器阵列平面。每个平面可以单独制造，并且平面内的每个阵列可以单独启用/禁用。以这种方式，可以单独地测试平面内的每个存储器阵列，并且可以整理出有缺陷的存储器阵列，这增加了最终的产量和质量。存储器平面可以堆叠在彼此的顶部并且在有源电路平面的顶部上以形成大容量存储器件。通过使用适当的存储器单元作为基本单元，存储器可以是易失性的或非易失性的。此外，存储器平面可以与有源电路分开制造。因此，存储器平面不需要硅衬底，并且可以由例如玻璃衬底形成。此外，每个存储器平面可以经由平面存储器选择晶体管单独选择（或使能）。阵列可以通过阵列选择晶体管单独选择（或使能）。这些晶体管可以由非晶硅晶体管和/或薄膜晶体管形成。数据总线，阵列选择总线和平面选择总线通过每个平面上的侧接触垫在存储器平面和有源电路平面之间提供电连接。 3-D内存大容量存储。存储器可以由一个或多个平面形成，每个平面包括一个或多个存储器阵列。每个平面的每个存储器阵列可以单独启用或禁用。存储器阵列可以形成在硅或非硅基衬底上。可以在存储器阵列和平面之间共享有源电路平面以执行读取和写入功能。

8. 发明授权

US06673714B2 Method of fabricating a sub-lithographic sized via 有权
标题翻译：制造亚光刻尺寸通孔的方法
公开(公告)号：US06673714B2
公开(公告)日：2004-01-06
申请号：US10133605
申请日：2002-04-25
申请人： Heon Lee , Thomas C. Anthony , Lung T. Tran
发明人： Heon Lee , Thomas C. Anthony , Lung T. Tran
IPC分类号： H01L214763
CPC分类号： H01L21/0338 , H01L21/0273 , H01L21/0337 , Y10S438/947
摘要： A method of fabricating a sub-lithographic sized via is disclosed. A dual-polymer method is used to form a stacked layer of polymer materials wherein a first polymer layer has a first etch rate and a second polymer layer has a second etch rate. The first etch rate is preselected to be faster than the second etch rate when the first and second polymer layers are isotropically etched. The second polymer layer is made from a photo active material and is operative as an etch mask for the first photoresist layer. The etching is continued until the first polymer layer has a sub-lithographic feature size that is less than a lithography limit of a lithography system. A dielectric material is deposited on the etch mask and the first polymer layer. The first polymer layer is lifted-off to define a sub-lithographic sized via.
摘要翻译：公开了一种制造亚光刻尺寸的通孔的方法。使用双聚合物方法形成聚合物材料的堆叠层，其中第一聚合物层具有第一蚀刻速率，第二聚合物层具有第二蚀刻速率。当第一和第二聚合物层被各向同性蚀刻时，预先选择第一蚀刻速率快于第二蚀刻速率。第二聚合物层由光活性材料制成，并且可用作第一光致抗蚀剂层的蚀刻掩模。继续蚀刻直到第一聚合物层具有小于光刻系统的光刻极限的亚光刻特征尺寸。介电材料沉积在蚀刻掩模和第一聚合物层上。第一聚合物层被剥离以确定亚光刻尺寸的通孔。

9. 发明授权

US06607924B2 Solid-state memory with magnetic storage cells 有权
公开(公告)号：US06607924B2
公开(公告)日：2003-08-19
申请号：US09871387
申请日：2001-05-31
申请人： James A. Brug , Lung T. Tran , Thomas C. Anthony , Manoj K. Bhattacharyya , Janice Nickel
发明人： James A. Brug , Lung T. Tran , Thomas C. Anthony , Manoj K. Bhattacharyya , Janice Nickel
IPC分类号： H01L2100
CPC分类号： H01L43/12 , B82Y10/00 , G11C11/15 , H01L27/224
摘要： A solid-state memory including an array of magnetic storage cells and a set of conductors. The process steps that pattern the conductors also patterns the magnetic layers in the magnetic storage cells thereby avoiding the need to employ precise alignment between pattern masks.

10. 发明授权

US06584029B2 One-time programmable memory using fuse/anti-fuse and vertically oriented fuse unit memory cells 失效
标题翻译：一次性可编程存储器，使用保险丝/反熔丝和垂直取向的熔丝单元存储单元
公开(公告)号：US06584029B2
公开(公告)日：2003-06-24
申请号：US09924577
申请日：2001-08-09
申请人： Lung T. Tran , Thomas C. Anthony , Frederick A. Perner
发明人： Lung T. Tran , Thomas C. Anthony , Frederick A. Perner
IPC分类号： G11C700
CPC分类号： H01L23/5252 , G11C13/0004 , G11C17/16 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A one-time programmable (“OTP”) memory includes one or more memory arrays stacked on top of each other. The OTP memory array is a cross-point array where unit memory cells are formed at the cross-points. The unit memory cell may include a fuse and an anti-fuse in series with each other or may include a vertically oriented fuse. Programming the memory may include the steps of selecting unit memory cells, applying a writing voltage such that critical voltage drop across the selected cells occur. This causes the anti-fuse of the cell to break down to a low resistance. The low resistance of the anti-fuse causes a high current pulse to be delivered to the fuse, which in turn melts the fuse to an open state. Reading the memory may include the steps of selecting unit memory cells for reading, applying a reading voltage to the selected memory cells and measuring whether current is present or not. Equipotential sensing may be used to read the memory.
摘要翻译：一次性可编程（“OTP”）存储器包括堆叠在彼此之上的一个或多个存储器阵列。 OTP存储器阵列是在交叉点处形成单位存储单元的交叉点阵列。单元存储单元可以包括彼此串联的保险丝和反熔丝，或者可以包括垂直定向的保险丝。对存储器进行编程可以包括选择单元存储器单元，施加写入电压以使得跨所选单元格出现临界电压降的步骤。这使得电池的反熔丝分解成低电阻。反熔丝的低电阻导致高电流脉冲被输送到保险丝，熔丝将熔丝熔化成打开状态。读取存储器可以包括以下步骤：选择用于读取的单元存储单元，向所选存储单元施加读取电压并测量是否存在电流。等电位感测可用于读取存储器。

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