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1. 发明授权

US08883600B1 Transistor having reduced junction leakage and methods of forming thereof 有权
标题翻译：具有减少的结漏电的晶体管及其形成方法
公开(公告)号：US08883600B1
公开(公告)日：2014-11-11
申请号：US13725152
申请日：2012-12-21
申请人： Scott E. Thompson , Lucian Shifren , Pushkar Ranade , Yujie Liu , Sung Hwan Kim , Lingquan Wang , Dalong Zhao , Teymur Bakhishev , Thomas Hoffmann , Sameer Pradhan , Michael Duane
发明人： Scott E. Thompson , Lucian Shifren , Pushkar Ranade , Yujie Liu , Sung Hwan Kim , Lingquan Wang , Dalong Zhao , Teymur Bakhishev , Thomas Hoffmann , Sameer Pradhan , Michael Duane
IPC分类号： H01L21/331 , H01L29/66 , H01L29/78
CPC分类号： H01L29/7833 , H01L21/823814 , H01L21/823821 , H01L29/0847 , H01L29/1041 , H01L29/105 , H01L29/1083 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7836
摘要： A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.
摘要翻译：晶体管及其制造方法包括至少部分地形成在沟道层和栅极堆叠下方的半导体衬底中的屏蔽层，栅极堆叠包括在栅极叠层的任一侧上的间隔结构。晶体管包括沟道层中的浅掺杂稀土漏极区和相对于屏蔽层底部的深度处的深掺杂漏极区，用于减少结漏电流。还可以包括补偿层以防止背栅控制的损失。

2. 发明授权

US08748986B1 Electronic device with controlled threshold voltage 有权
标题翻译：具有受控阈值电压的电子设备
公开(公告)号：US08748986B1
公开(公告)日：2014-06-10
申请号：US13559554
申请日：2012-07-26
申请人： Lucian Shifren , Pushkar Ranade
发明人： Lucian Shifren , Pushkar Ranade
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/786 , H01L29/78609 , H01L29/78612 , H01L29/78696
摘要： Structures and methods of fabrication thereof related to an improved semiconductor on insulator (SOI) transistor formed on an SOI substrate. The improved SOI transistor includes a substantially undoped channel extending between the source and the drain, an optional threshold voltage set region positioned below the substantially undoped channel, and a screening region positioned below the threshold voltage set region. The threshold voltage of the improved SOI transistor can be adjusted without halo implants or threshold voltage implants into the channel, using the position and/or dopant concentration of the screening region and/or the threshold voltage set region.
摘要翻译：其结构及其制造方法涉及形成在SOI衬底上的改进的绝缘体上半导体（SOI）晶体管。改进的SOI晶体管包括在源极和漏极之间延伸的基本上未掺杂的沟道，位于基本上未掺杂沟道下方的可选阈值电压设置区域和位于阈值电压设置区域下方的屏蔽区域。可以使用屏蔽区域和/或阈值电压设置区域的位置和/或掺杂剂浓度来调整改进的SOI晶体管的阈值电压而无需光晕注入或阈值电压注入到沟道中。

3. 发明申请

US20130161743A1 SOURCE/DRAIN EXTENSION CONTROL FOR ADVANCED TRANSISTORS 有权
标题翻译：高级晶体管的源/漏极扩展控制
公开(公告)号：US20130161743A1
公开(公告)日：2013-06-27
申请号：US13770313
申请日：2013-02-19
申请人： Pushkar Ranade , Lucian Shifren , Sachin R. Sonkusale
发明人： Pushkar Ranade , Lucian Shifren , Sachin R. Sonkusale
IPC分类号： H01L29/78 , H01L27/085
CPC分类号： H01L29/7816 , H01L27/085 , H01L27/088 , H01L29/105 , H01L29/1083 , H01L29/165 , H01L29/66537 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7835 , H01L29/7848
摘要： A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×1019 atoms/cm3′, or alternatively, less than one-quarter the dopant concentration of the source and the drain.
摘要翻译：具有改进性能的平面晶体管在半导体衬底上具有源极和漏极，其包括在源极和漏极之间延伸的基本上未掺杂的沟道。栅极位于衬底上的基本上未掺杂的沟道上。注入源极/漏极延伸部接触源极和漏极，注入源极/漏极延伸部的掺杂剂浓度小于约1×1019原子/ cm3'，或者可选地，小于源极的掺杂剂浓度的四分之一，以及排水。

4. 发明申请

US20110121404A1 ADVANCED TRANSISTORS WITH PUNCH THROUGH SUPPRESSION 有权
标题翻译：先进的晶体管通过抑制通过PUNCH
公开(公告)号：US20110121404A1
公开(公告)日：2011-05-26
申请号：US12895813
申请日：2010-09-30
申请人： Lucian Shifren , Pushkar Ranade , Paul E. Gregory , Sachin R. Sonkusale , Weimin Zhang
发明人： Lucian Shifren , Pushkar Ranade , Paul E. Gregory , Sachin R. Sonkusale , Weimin Zhang
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/1083 , H01L21/823412 , H01L21/82345 , H01L21/823493 , H01L27/088 , H01L27/092 , H01L29/0847 , H01L29/1033 , H01L29/1045 , H01L29/36 , H01L29/66537 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7836
摘要： An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.
摘要翻译：具有穿通抑制的高级晶体管包括具有长度为Lg的阱，阱掺杂以具有掺杂剂的第一浓度，以及位于栅极下方并具有第二掺杂浓度的屏蔽区域。掺杂剂的第二浓度可以大于每立方厘米5×1018个掺杂剂原子。在筛选区域和井之间的栅极下方设置有至少一个穿孔抑制区域。穿通抑制区域具有在第一浓度和第二浓度掺杂剂之间的掺杂剂的第三浓度。可以将偏置电压施加到阱区域以调整晶体管的阈值电压。

5. 发明授权

US08963249B1 Electronic device with controlled threshold voltage 有权
标题翻译：具有受控阈值电压的电子设备
公开(公告)号：US08963249B1
公开(公告)日：2015-02-24
申请号：US14292806
申请日：2014-05-30
申请人： Lucian Shifren , Pushkar Ranade
发明人： Lucian Shifren , Pushkar Ranade
IPC分类号： H01L27/01 , H01L27/12 , H01L29/76 , H01L29/94 , H01L31/0392 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/786
CPC分类号： H01L29/786 , H01L29/78609 , H01L29/78612 , H01L29/78696
摘要： A field effect transistor having a source, drain, and a gate can include a semiconductor substrate, a buried insulator layer positioned on the semiconductor substrate, and a semiconductor overlayer positioned on the buried insulator layer; a low dopant channel region positioned below the gate and between the source and the drain and in an upper portion of the semiconductor overlayer; and a plurality of doped regions having a predetermined dopant concentration profile, including a screening region positioned in the semiconductor overlayer below the low dopant channel region, the screening region extending toward the buried insulator layer, and a threshold voltage set region positioned between the screening region and the low dopant channel, the screening region and the threshold voltage set region having each a peak dopant concentration, the threshold voltage region peak dopant concentration being between 1/50 and ½ of the peak dopant concentration of the screening region.
摘要翻译：具有源极，漏极和栅极的场效应晶体管可以包括半导体衬底，位于半导体衬底上的掩埋绝缘体层和位于掩埋绝缘体层上的半导体覆层; 位于栅极下方以及源极和漏极之间以及位于半导体覆盖层的上部的低掺杂剂沟道区; 以及具有预定掺杂剂浓度分布的多个掺杂区域，包括位于低掺杂剂沟道区域之下的半导体覆盖层中的屏蔽区域，朝向掩埋绝缘体层延伸的屏蔽区域，以及位于屏蔽区域之间的阈值电压设置区域和低掺杂剂通道，筛选区域和阈值电压设置区域各自具有峰值掺杂剂浓度，阈值电压区域峰值掺杂剂浓度在筛选区域的峰值掺杂剂浓度的1/50和1/2之间。

6. 发明授权

US08759872B2 Transistor with threshold voltage set notch and method of fabrication thereof 有权
标题翻译：具有阈值电压设置陷波器的晶体管及其制造方法
公开(公告)号：US08759872B2
公开(公告)日：2014-06-24
申请号：US12971955
申请日：2010-12-17
申请人： Reza Arghavani , Pushkar Ranade , Lucian Shifren , Scott E. Thompson , Catherine de Villeneuve
发明人： Reza Arghavani , Pushkar Ranade , Lucian Shifren , Scott E. Thompson , Catherine de Villeneuve
IPC分类号： H01L21/336 , H01L21/338
CPC分类号： H01L27/0921 , H01L21/823412 , H01L21/82345 , H01L21/823493 , H01L21/823807 , H01L21/823842 , H01L21/823878 , H01L21/823892 , H01L27/088 , H01L27/092 , H01L29/0653 , H01L29/105 , H01L29/1083 , H01L29/36 , H01L29/365 , H01L29/4966 , H01L29/66537 , H01L29/6659 , H01L29/7833 , H01L29/7836
摘要： A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the VT setting within a precise range. This VT set range may be extended by appropriate selection of metals so that a very wide range of VT settings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control VT (with a low σVT) and VDD, so that the body bias can be tuned separately from VT for a given device.
摘要翻译：其制造的结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有减小的VT，并且可以允许在沟道区中具有掺杂剂的FET的阈值电压VT 更精确地设置。指示特征性缺口的新型掺杂物分布使得能够在精确范围内调整VT设置。可以通过适当选择金属来扩展该VT设定范围，使得在管芯上容纳非常宽范围的VT设置。与传统的体积CMOS晶体管相比，DDC设计也可以具有强大的机身效应，可以显着地动态控制DDC晶体管的功耗。结果是能够独立地控制VT（具有低电平（VT））和VDD（VDD），从而使给定器件的体偏压可以与VT分开调谐。

7. 发明授权

US08569128B2 Semiconductor structure and method of fabrication thereof with mixed metal types 有权
公开(公告)号：US08569128B2
公开(公告)日：2013-10-29
申请号：US12960266
申请日：2010-12-03
申请人： Lucian Shifren , Pushkar Ranade , Sachin R. Sonkusale
发明人： Lucian Shifren , Pushkar Ranade , Sachin R. Sonkusale
IPC分类号： H01L21/823842 , H01L21/823807
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823842 , H01L27/0922
摘要： A semiconductor structure includes a first PMOS transistor element having a gate region with a first gate metal associated with a PMOS work function and a first NMOS transistor element having a gate region with a second metal associated with a NMOS work function. The first PMOS transistor element and the first NMOS transistor element form a first CMOS device. The semiconductor structure also includes a second PMOS transistor that is formed in part by concurrent deposition with the first NMOS transistor element of the second metal associated with a NMOS work function to form a second CMOS device with different operating characteristics than the first CMOS device.

8. 发明授权

US08530286B2 Low power semiconductor transistor structure and method of fabrication thereof 有权
标题翻译：低功率半导体晶体管结构及其制造方法
公开(公告)号：US08530286B2
公开(公告)日：2013-09-10
申请号：US12971884
申请日：2010-12-17
申请人： Lucian Shifren , Pushkar Ranade , Scott E. Thompson , Sachin R. Sonkusale , Weimin Zhang
发明人： Lucian Shifren , Pushkar Ranade , Scott E. Thompson , Sachin R. Sonkusale , Weimin Zhang
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823878 , H01L21/823892 , H01L29/7833
摘要： A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.
摘要翻译：其制造的结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有降低的sigmaVT，并且可以允许在沟道区中具有掺杂剂的FET的阈值电压VT被设置更准确地说与传统的体积CMOS晶体管相比，DDC设计也可以具有强大的机身效应，可以显着地动态控制DDC晶体管的功耗。半导体结构包括模拟器件和数字器件，每个器件和数字器件均具有外延沟道层，其中单个栅极氧化层位于数字器件的NMOS和PMOS晶体管元件的外延沟道层上，并且双栅极和三栅极氧化层之一是在模拟器件的NMOS和PMOS晶体管元件的外延沟道层上。

9. 发明授权

US09406567B1 Method for fabricating multiple transistor devices on a substrate with varying threshold voltages 有权
标题翻译：在具有不同阈值电压的衬底上制造多个晶体管器件的方法
公开(公告)号：US09406567B1
公开(公告)日：2016-08-02
申请号：US13407527
申请日：2012-02-28
申请人： Lucian Shifren , Pushkar Ranade , Thomas Hoffmann , Scott E. Thompson
发明人： Lucian Shifren , Pushkar Ranade , Thomas Hoffmann , Scott E. Thompson
IPC分类号： H01L21/8238 , H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823412 , H01L21/823493 , H01L21/823892
摘要： Fabrication of a first device on a substrate is performed by exposing a first device region, removing a portion of the substrate to create a trench in the first device region, forming a screen layer with a first dopant concentration in the trench on the substrate, and forming an epitaxial channel on the screen layer having a first thickness. On or more other devices are similarly formed on the substrate independent of each other with epitaxial channels of different thicknesses than the first thickness. Devices with screen layers having the same dopant concentration but with different epitaxial channel thicknesses have different threshold voltages. Thus, a wide variety of threshold voltage devices can be formed on the same substrate. Further threshold voltage setting can be achieved through variations in the dopant concentration of the screen layers.
摘要翻译：通过暴露第一器件区域，去除衬底的一部分以在第一器件区域中形成沟槽，在衬底上的沟槽中形成具有第一掺杂剂浓度的屏蔽层，从而在衬底上制造第一器件，以及在具有第一厚度的屏幕层上形成外延沟道。在衬底上类似地形成一个或多个其它器件，彼此独立地具有不同于第一厚度的厚度的外延沟道。具有相同掺杂浓度但具有不同外延沟道厚度的屏幕层的器件具有不同的阈值电压。因此，可以在同一衬底上形成各种阈值电压器件。可以通过屏幕层的掺杂剂浓度的变化来实现进一步的阈值电压设定。

10. 发明授权

US08563384B2 Source/drain extension control for advanced transistors 有权
标题翻译：高级晶体管的源/漏扩展控制
公开(公告)号：US08563384B2
公开(公告)日：2013-10-22
申请号：US13770313
申请日：2013-02-19
申请人： Pushkar Ranade , Lucian Shifren , Sachin R. Sonkusale
发明人： Pushkar Ranade , Lucian Shifren , Sachin R. Sonkusale
IPC分类号： H01L21/336 , H01L21/70 , H01L29/02
CPC分类号： H01L29/7816 , H01L27/085 , H01L27/088 , H01L29/105 , H01L29/1083 , H01L29/165 , H01L29/66537 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7835 , H01L29/7848
摘要： A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×1019 atoms/cm3′, or alternatively, less than one-quarter the dopant concentration of the source and the drain.
摘要翻译：具有改进性能的平面晶体管在半导体衬底上具有源极和漏极，其包括在源极和漏极之间延伸的基本上未掺杂的沟道。栅极位于衬底上的基本上未掺杂的沟道上。注入源极/漏极延伸部接触源极和漏极，注入源极/漏极延伸部的掺杂剂浓度小于约1×1019原子/ cm3'，或者可选地，小于源极的掺杂剂浓度的四分之一，以及排水。

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