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1. 发明授权

US5276862A Safestore frame implementation in a central processor 失效
标题翻译：在中央处理器中实现Safestore框架
公开(公告)号：US5276862A
公开(公告)日：1994-01-04
申请号：US682801
申请日：1991-04-09
申请人： Lowell D. McCulley , Russell W. Guenthner , Clinton B. Eckard , Leonard Rabins , William A. Shelly , Ronald E. Lange , David S. Edwards
发明人： Lowell D. McCulley , Russell W. Guenthner , Clinton B. Eckard , Leonard Rabins , William A. Shelly , Ronald E. Lange , David S. Edwards
IPC分类号： G06F11/14 , G06F11/16 , G06F11/00
CPC分类号： G06F11/1441 , G06F11/1641 , G06F11/1637
摘要： In order to gather, store temporarily and deliver (if needed) central processor safestore information, a multiphase clock is employed to capture (one full clock cycle behind) the safestore information which typically includes all software visible registers in all (or selected) data manipulation chips of the CPU by routing the safestore information through temporary storage (under the influence of the multiphase clock) in a cache data array and into a special purpose XRAM module. Thus, upon the sensing of a fault, valid safestore information is available in the XRAM for analysis and, if appropriate, resumption of operation at a sequential point just previous to that at which the fault occurred.
摘要翻译：为了收集，存储和交付（如果需要的话）中央处理器保险箱信息，采用多相时钟来捕获（一个完整的时钟周期）保存存储信息，这些信息通常包括所有（或选定的）数据操作中的所有软件可见寄存器通过临时存储（在多相时钟的影响下）将缓存存储信息路由到高速缓存数据阵列中并进入特殊目的XRAM模块，从而使CPU的芯片。因此，在检测到故障时，XRAM中有效的保险箱信息可用于分析，如果适用，在刚刚发生故障的连续点恢复运行。

2. 发明授权

US5263034A Error detection in the basic processing unit of a VLSI central processor 失效
标题翻译： VLSI中央处理器的基本处理单元中的错误检测
公开(公告)号：US5263034A
公开(公告)日：1993-11-16
申请号：US594880
申请日：1990-10-09
申请人： Russell W. Guenthner , Clinton B. Eckard , Leonard Rabins , William A. Shelly , Ronald E. Lange , David S. Edwards , Bruce E. Flocken
发明人： Russell W. Guenthner , Clinton B. Eckard , Leonard Rabins , William A. Shelly , Ronald E. Lange , David S. Edwards , Bruce E. Flocken
IPC分类号： G06F11/16
CPC分类号： G06F11/1641
摘要： In order to provide efficient error detection in a central processor's Basic Processing Unit (BPU) including an AX (address and execution) module, a DN (decimal numeric) module and an FP (floating point) module, each module is provided redundantly in a master/slave pair, and the local result of data manipulation operations performed in each pair are compared for identity before the results are validated for subsequent use in the central processor.
摘要翻译：为了在包括AX（地址和执行）模块，DN（十进制数字）模块和FP（浮点））模块的中央处理器的基本处理单元（BPU）中提供有效的错误检测，每个模块在主/从对，并且将每个对中执行的数据操作操作的本地结果进行比较，以便在结果被验证以供后续在中央处理器中使用之前进行身份验证。

3. 发明授权

US5367699A Central processing unit incorporation selectable, precisa ratio, speed of execution derating 失效
标题翻译：中央处理单元合并可选择，准确率，执行速度降额
公开(公告)号：US5367699A
公开(公告)日：1994-11-22
申请号：US800343
申请日：1991-11-26
申请人： Ronald E. Lange , Russell W. Guenthner , Leonard Rabins
发明人： Ronald E. Lange , Russell W. Guenthner , Leonard Rabins
IPC分类号： G06F9/30 , G06F9/38 , G06F7/62
CPC分类号： G06F9/3873 , G06F9/3836 , G06F9/3869
摘要： In order to obtain precise submodel control in a central processing unit, there is provided a subcounter which is controlled to count up from a beginning count as an instruction is executed and to count back down at the same rate to the reference count to obtain an effective delay before processing of the next instruction to be processed during normal program execution is started. Instruction transfer and decoding of the new instruction entering the pipeline is inhibited until the subcounter's most significant bit ("sign bit") changes state. If the subcounter is allowed to count during the entire count up and count down periods, a derated mode of 1/2 is achieved. To obtain other fractions, the subcounter is controlled to count periodically during one count direction period and to count full time during the other count direction period. In the exemplary embodiment, 1/4 and 3/4 derating is selectively achieved by the use of a modulo 3 counter which allows the subcounter to count only 1/3 the time in one or the other of the subcounter count up or count down periods.
摘要翻译：为了在中央处理单元中获得精确的子模型控制，提供了一个子计数器，其被控制为从执行指令开始计数开始计数，并以与参考计数相同的速率向下计数以获得有效的开始在正常程序执行期间处理下一个待处理指令之前的延迟。禁止进入管道的新指令的指令传输和解码，直到子计数器的最高有效位（“符号位”）改变状态。如果在整个计数和倒计时期间允许子计数器进行计数，则实现1/2的降额模式。为了获得其他分数，子计数器被控制以在一个计数方向期间周期性地计数，并且在另一个计数方向周期期间计数全时间。在示例性实施例中，通过使用模3计数器来选择性地实现1/4和3/4降额，所述模3计数器允许次计数器仅对次计数器的一个或另一个中的时间进行计数，。

4. 发明授权

US5644761A Basic operations synchronization and local mode controller in a VLSI central processor 失效
标题翻译： VLSI中央处理器中的基本操作同步和本地模式控制器
公开(公告)号：US5644761A
公开(公告)日：1997-07-01
申请号：US893871
申请日：1992-06-05
申请人： Ronald W. Yoder , Ronald E. Lange , William A. Shelly , Russell W. Guenthner , Richard L. Demers
发明人： Ronald W. Yoder , Ronald E. Lange , William A. Shelly , Russell W. Guenthner , Richard L. Demers
IPC分类号： G06F9/26 , G06F9/22
CPC分类号： G06F9/267
摘要： In order to efficiently undertake the micro-steps required to execute an extended instruction in a central processing unit, a main sequence controller and a separate basic operations controller having its own sequencer and the ability to run semi-autonomously are provided. Normally, the main sequence controller determines the operation of the basic operations controller, but, in the case of execution of, for example, a multi-word instruction requiring extended basic operations, the basic operations controller temporarily takes control over the main controller until the extended basic operations have been completed. The result is a relatively simple sequencer that supports tight micro-coded functions where many of the sequence decisions can be predetermined.
摘要翻译：为了有效地执行在中央处理单元中执行扩展指令所需的微步骤，提供了具有其自己的定序器的主序列控制器和单独的基本操作控制器以及半自主运行的能力。通常，主序列控制器确定基本操作控制器的操作，但是在执行例如需要扩展基本操作的多字指令的情况下，基本操作控制器暂时控制主控制器，直到扩展基本操作已经完成。结果是相对简单的定序器，其支持紧密的微编码功能，其中许多顺序决定可以被预先确定。

5. 发明授权

US08869126B2 Method and apparatus enabling multi threaded program execution for a Cobol program including OpenMP directives by utilizing a two-stage compilation process 有权
标题翻译：通过利用两阶段编译过程，可以实现包括OpenMP指令在内的Cobol程序的多线程程序执行的方法和装置
公开(公告)号：US08869126B2
公开(公告)日：2014-10-21
申请号：US13729490
申请日：2012-12-28
申请人： Cynthia S. Guenthner , Russell W. Guenthner , John Edward Heath , Albert Henry John Wigchert , F. Michel Brown , Nicholas John Colasacco , Clinton B. Eckard
发明人： Cynthia S. Guenthner , Russell W. Guenthner , John Edward Heath , Albert Henry John Wigchert , F. Michel Brown , Nicholas John Colasacco , Clinton B. Eckard
IPC分类号： G06F9/45
CPC分类号： G06F8/456
摘要： A method and apparatus is disclosed for compilation of an original Cobol program with support for improved performance by increased parallelism during execution using multiple threads of processing. The approach includes a two stage compilation process, the first compilation/translation step by a first specialized compiler/translator that takes as input a Cobol source program that includes parallelization directives, and produces as output an intermediate computer program in a second computer programming language, the intermediate program including parallelization directives in the second computer programming language. The intermediate program is then compiled utilizing a selected second compiler that provides support for parallelism described in the second programming language. The approach optionally allows for use of pragmas serving as parallelization directives to the compiler in the original Cobol program or in the intermediate program.
摘要翻译：公开了一种用于编译原始Cobol程序的方法和装置，其支持通过使用多个处理线程在执行期间通过增加的并行性来提高性能。该方法包括两阶段编译过程，第一个专业编译器/翻译器的第一个编译/翻译步骤，将包含并行化指令的Cobol源程序作为输入，并以第二计算机编程语言生成中间计算机程序作为输出，中间程序包括第二计算机编程语言中的并行化指令。然后使用提供对第二编程语言中描述的并行性的支持的所选择的第二编译器来编译中间程序。该方法可以允许在原始Cobol程序或中间程序中使用用作并行指令的编译指示给编译器。

6. 发明授权

US08856759B2 Method and apparatus providing COBOL decimal type arithmetic functions with improved performance 有权
标题翻译：提供具有改进性能的COBOL十进制算术函数的方法和装置
公开(公告)号：US08856759B2
公开(公告)日：2014-10-07
申请号：US12658017
申请日：2010-02-01
申请人： Russell W. Guenthner , Clinton B. Eckard
发明人： Russell W. Guenthner , Clinton B. Eckard
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F8/49 , G06F8/41 , G06F8/4441 , G06F9/4484
摘要： A method and apparatus is disclosed providing an improvement in performance for arithmetic computations by a computer system for calculations which include decimal numeric variables. The improvement in at least one embodiment includes use of a special compiler in cooperation with a special decimal numeric subroutine library. The compiler provides comparative alignment information based upon comparing alignments of a plurality of decimal variables. The decimal subroutine library can then provide improved performance at run time by utilizing the information compared by the compiler at compiler time rather than making those computations repeatedly at run time.
摘要翻译：公开了一种方法和装置，其通过计算机系统提供包括十进制数字变量的计算的算术计算性能的改进。至少一个实施例的改进包括与特殊的十进制数字子程序库协同使用特殊的编译器。编译器基于比较多个十进制变量的比对来提供比较对齐信息。然后，十进制子程序库可以通过利用编译器在编译器时比较的信息在运行时提供改进的性能，而不是在运行时重复进行这些计算。

7. 发明申请

US20110191755A1 Method and apparatus providing COBOL decimal type arithmetic functions with improved performance 有权
标题翻译：提供具有改进性能的COBOL十进制算术函数的方法和装置
公开(公告)号：US20110191755A1
公开(公告)日：2011-08-04
申请号：US12658017
申请日：2010-02-01
申请人： Russell W. Guenthner , Clinton B. Eckard
发明人： Russell W. Guenthner , Clinton B. Eckard
IPC分类号： G06F9/45
CPC分类号： G06F8/49 , G06F8/41 , G06F8/4441 , G06F9/4484
摘要： A method and apparatus is disclosed providing an improvement in performance for arithmetic computations by a computer system for calculations which include decimal numeric variables. The improvement in at least one embodiment includes use of a special compiler in cooperation with a special decimal numeric subroutine library. The compiler provides comparative alignment information based upon comparing alignments of a plurality of decimal variables. The decimal subroutine library can then provide improved performance at run time by utilizing the information compared by the compiler at compiler time rather than making those computations repeatedly at run time.
摘要翻译：公开了一种方法和装置，其通过计算机系统提供包括十进制数字变量的计算的算术计算性能的改进。至少一个实施例的改进包括与特殊的十进制数字子程序库协同使用特殊的编译器。编译器基于比较多个十进制变量的比对来提供比较对齐信息。然后，十进制子程序库可以通过利用编译器在编译器时比较的信息在运行时提供改进的性能，而不是在运行时重复进行这些计算。

8. 发明授权

US09182962B2 Method for translating a cobol source program into readable and maintainable program code in an object oriented second programming language 有权
标题翻译：将cobol源程序转换为面向对象的第二编程语言中的可读和可维护程序代码的方法
公开(公告)号：US09182962B2
公开(公告)日：2015-11-10
申请号：US13314041
申请日：2011-12-07
申请人： Todd Bradley Kneisel , Cynthia S. Guenthner , Albert Henry John Wigchert , Nicholas John Colasacco , Russell W. Guenthner , John Edward Heath , Clinton B. Eckard
发明人： Todd Bradley Kneisel , Cynthia S. Guenthner , Albert Henry John Wigchert , Nicholas John Colasacco , Russell W. Guenthner , John Edward Heath , Clinton B. Eckard
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/51 , G06F8/31
摘要： A method is disclosed for translating by a computer system of a COBOL computer program into a translated computer program in a readable and maintainable syntax in an object oriented programming language. The translated program including variable names equivalent to the original COBOL variable names and with attributes described in COBOL syntax. The translating method further providing for memory allocation in the translated computer program for storage of “COBOL” variables compatible with that of the original COBOL program; a description of program flow that is readable, and utilizing arithmetic operators to describe operations between COBOL variables. Also disclosed is a special object oriented run-time library for creating and performing operations between COBOL numeric objects, including maintaining storage of variable content in the original COBOL format, and for enabling readability of the translated source code by allowing arguments for variable type descriptions to be expressed in COBOL syntax.
摘要翻译：公开了一种通过计算机系统将COBOL计算机程序翻译成面向对象编程语言的可读和可维护语法的翻译计算机程序的方法。翻译的程序包括与原始COBOL变量名称等效的变量名称，并具有COBOL语法中描述的属性。翻译方法进一步提供翻译的计算机程序中的存储器分配，用于存储与原始COBOL程序兼容的“COBOL”变量; 描述可读的程序流程，并利用算术运算符来描述COBOL变量之间的操作。还公开了一种特殊的面向对象的运行时库，用于在COBOL数字对象之间创建和执行操作，包括保持原始COBOL格式的可变内容的存储，以及通过允许变量类型描述的参数来实现所翻译的源代码的可读性用COBOL语法表达。

9. 发明申请

US20140189663A1 METHOD AND APPARATUS ENABLING MULTI THREADED PROGRAM EXECUTION FOR A COBOL PROGRAM INCLUDING OPENMP DIRECTIVES BY UTILIZING A TWO-STAGE COMPILATION PROCESS 有权
标题翻译：方法和装置通过利用两阶段编译过程实现包括OPENMP指令的COBOL程序的多线程程序执行
公开(公告)号：US20140189663A1
公开(公告)日：2014-07-03
申请号：US13729490
申请日：2012-12-28
申请人： Cynthia S. Guenthner , Russell W. Guenthner , John Edward Heath , Albert Henry John Wigchert , F. Michel Brown , Nicholas John Colasacco , Clinton B. Eckard
发明人： Cynthia S. Guenthner , Russell W. Guenthner , John Edward Heath , Albert Henry John Wigchert , F. Michel Brown , Nicholas John Colasacco , Clinton B. Eckard
IPC分类号： G06F9/45
CPC分类号： G06F8/456
摘要： A method and apparatus is disclosed for compilation of an original Cobol program with support for improved performance by increased parallelism during execution using multiple threads of processing. The approach includes a two stage compilation process, the first compilation/translation step by a first specialized compiler/translator that takes as input a Cobol source program that includes parallelization directives, and produces as output an intermediate computer program in a second computer programming language, the intermediate program including parallelization directives in the second computer programming language. The intermediate program is then compiled utilizing a selected second compiler that provides support for parallelism described in the second programming language. The approach optionally allows for use of pragmas serving as parallelization directives to the compiler in the original Cobol program or in the intermediate program.
摘要翻译：公开了一种用于编译原始Cobol程序的方法和装置，其支持通过使用多个处理线程在执行期间通过增加的并行性来提高性能。该方法包括两阶段编译过程，第一个专业编译器/翻译器的第一个编译/翻译步骤，将包含并行化指令的Cobol源程序作为输入，并以第二计算机编程语言生成中间计算机程序作为输出，中间程序包括第二计算机编程语言中的并行化指令。然后使用提供对第二编程语言中描述的并行性的支持的所选择的第二编译器来编译中间程序。该方法可以允许在原始Cobol程序或中间程序中使用用作并行指令的编译指示给编译器。

10. 发明授权

US07809547B2 Host computer system emulating target system legacy software and providing for incorporating more powerful application program elements into the flow of the legacy software 失效
标题翻译：主机计算机系统模拟目标系统遗留软件，并提供将更强大的应用程序元素并入到传统软件的流程中
公开(公告)号：US07809547B2
公开(公告)日：2010-10-05
申请号：US11324052
申请日：2005-12-29
申请人： Russell W. Guenthner , David W. Selway , Stefan R. Bohult , Clinton B. Eckard
发明人： Russell W. Guenthner , David W. Selway , Stefan R. Bohult , Clinton B. Eckard
IPC分类号： G06F9/455 , G06F9/45 , G06F9/44 , G06F9/00 , G06F9/04
CPC分类号： G06F9/455
摘要： As manufacturers of very fast and powerful commodity processors continue to improve the capabilities of their products, it has become practical to emulate the proprietary hardware and operating systems of powerful older computers on platforms built using commodity processors such that the manufacturers of the older computers can provide new systems which allow their customers to continue to use their highly-regarded proprietary legacy software on state-of-the-art new computer systems by emulating the older computer in software that runs on the new systems. In an example of the subject invention, a 64-bit Cobol Virtual Machine instruction provides the capability of adding to or improving the performance of legacy 36-bit Cobol code. Legacy Cobol instructions can be selectively diverted, in the host CPU, to a 64 bit Virtual Machine Implementation. The output legacy and new Cobol code is compiled in a dedicated implementation of the Cobol compiler, and the output of the special purpose compiler is emulated in a special purpose software emulator, separate from the main software emulator that handles the normal 36-bit stream of legacy code.
摘要翻译：随着非常快速和强大的商品处理器的制造商不断提高其产品的能力，在使用商品处理器构建的平台上模拟强大的旧版计算机的专有硬件和操作系统变得务实，这样老式计算机的制造商可以提供新系统允许他们的客户通过在新系统上运行的软件模拟旧的计算机，继续使用他们备受赞誉的专有遗留软件在最先进的新计算机系统上。在本发明的一个示例中，64位Cobol虚拟机指令提供添加或改善传统36位Cobol代码的性能的能力。传统Cobol指令可以在主机CPU中选择性转移到64位虚拟机实现。输出遗留和新的Cobol代码是在Cobol编译器的专用实现中编译的，专用编译器的输出在专用软件仿真器中仿真，与主软件仿真器分离，处理正常的36位流遗留代码

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