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1. 发明授权

US4821177A Apparatus for controlling system accesses having multiple command level conditional rotational multiple port servicing priority hierarchy 失效
标题翻译：用于控制具有多个命令级条件旋转多端口服务优先级层次的系统访问的装置
公开(公告)号：US4821177A
公开(公告)日：1989-04-11
申请号：US902545
申请日：1986-09-02
申请人： Robert J. Koegel , Leonard Rabins
发明人： Robert J. Koegel , Leonard Rabins
IPC分类号： G06F13/14 , G06F13/18
CPC分类号： G06F13/18
摘要： The apparatus controls access to at least one subsystem in response to requests for access from a plurality of equipments operatively connected to a corresponding port of said apparatus. The requests for access have a plurality of command levels wherein the command levels have a fixed predetermined priority relative to each other. The apparatus comprises a plurality of port request control elements for generating a plurality of specific request signals including a command level request signal to indicate the command level of a request received from the corresponding equipment, and a go signal to indicate the availability of the apparatus and the subsystem in order to execute the command requested. An activity priority select control element receives the specific request signals, and processes the go signals from each of the port request control elements to grant access within a predetermined time period to the equipment connected to the port having the highest port priority within the highest command level. There is also included logic which maintains a table of port priority for each command level utilized to determine a port priority within a command level. The table of port priority corresponding to the command level which was granted access is conditionally rotated when an equipment is granted access.

2. 发明授权

US5025370A Circuit for preventing lock-out of high priority requests to a system controller 失效
标题翻译：用于防止向系统控制器锁定高优先级请求的电路
公开(公告)号：US5025370A
公开(公告)日：1991-06-18
申请号：US902544
申请日：1986-09-02
申请人： Robert J. Koegel , Leonard Rabins
发明人： Robert J. Koegel , Leonard Rabins
IPC分类号： G06F11/00 , G06F11/07 , G06F13/364
CPC分类号： G06F11/076 , G06F11/073 , G06F11/0766 , G06F13/364
摘要： Lock-out of pending higher high priority requests to a system controller is prevented by a circuit which comprises a counter element for counting the number of times the pending higher high priority request is not granted access. The counting results in a count value which is temporarily stored in the counter element. A compare element compares the count value to a predetermined value, the predetermined value being a predetermined number of times the data processing system will permit bypassing the pending higher high priority request. A control signal is outputted from the compare element when the count value is equal to the predetermined value and is coupled to each port to inhibit any further request for access from the equipment from being accepted by the system controller. The circuit also includes a latch element for maintaining the control signal when it is determined that a subsequent high priority request which is granted access is not the highest high priority request, the control signal being maintained until all pending high priority requests have been granted access.
摘要翻译：通过包括用于计数未授权的较高优先级请求未被授予访问次数的计数器元件的电路来防止对系统控制器的等待更高的高优先级请求的锁定。该计数产生临时存储在计数元件中的计数值。比较元件将计数值与预定值进行比较，该预定值是数据处理系统允许绕过待处理的较高优先权请求的预定次数。当计数值等于预定值时，从比较元件输出控制信号，并耦合到每个端口，以阻止来自设备的进一步访问请求被系统控制器接受。该电路还包括用于在确定被授权接入的后续高优先级请求不是最高高优先级请求时保持控制信号的锁存元件，直到所有等待的高优先级请求被授权访问为止，才保持控制信号。

3. 发明授权

US5740350A Reconfigurable computer system 失效
标题翻译：可重构计算机系统
公开(公告)号：US5740350A
公开(公告)日：1998-04-14
申请号：US823663
申请日：1997-03-18
申请人： Leonard Rabins , David A. Bowman , David W. Selway , Clark D. McCaslin , Donald R. Kesner
发明人： Leonard Rabins , David A. Bowman , David W. Selway , Clark D. McCaslin , Donald R. Kesner
IPC分类号： G06F11/14 , G06F13/42 , G06F15/80 , G06F13/00 , G06F15/00
CPC分类号： G06F13/4269 , G06F11/1423 , G06F11/2028 , G06F11/2038 , G06F15/8007
摘要： A reconfigurable computer system which includes two computer subsystems, corresponding lines of the system busses of the two computer subsystems being interconnected by solid state switches. Each of the computer subsystems includes a control component, a service processor, which when an error is detected that would render the subsystem inoperative, causes the solid state switches to open to sever the connection between the system busses of the two computer subsystems so that the computer subsystem that has not suffered such a failure can continue to operate. A communication link is also established between the two service processors. Either, or both, service processors can sever the link between them.
摘要翻译：一种可重构计算机系统，其包括两个计算机子系统，两个计算机子系统的系统总线的对应线路由固态开关互连。每个计算机子系统包括控制组件，服务处理器，当检测到错误以使子系统不起作用时，导致固态开关断开以断开两个计算机子系统的系统总线之间的连接，使得没有遭受这种故障的计算机子系统可以继续运行。在两个服务处理器之间也建立通信链路。服务处理器或者两者都可以切断它们之间的链接。

4. 发明授权

US4037093A Matrix multiplier in GF(2.sup.m) 失效
标题翻译： GF中的矩阵乘法器（2 {HU m {b）
公开(公告)号：US4037093A
公开(公告)日：1977-07-19
申请号：US644776
申请日：1975-12-29
申请人： Gordon E. Gregg , Thomas H. Howell , Leonard Rabins
发明人： Gordon E. Gregg , Thomas H. Howell , Leonard Rabins
IPC分类号： G06F11/10 , G06F7/72 , H03M13/15 , G06F7/52
CPC分类号： H03M13/15 , G06F7/724
摘要： The invention comprises circuitry for systematically multiplying two arbitrary field elements in a Galois field GF(2.sup.m). Each element is represented by an m-bit binary number. The multiplicand field element is passed serially through a plurality of m-1 modulo multipliers. The multiplicand and the product from each of the m-1 modulo multipliers are passed through networks which are gated by bits of the multiplier field element forming partial products. The partial products are summed to form the bit representations of the final product.
摘要翻译：本发明包括用于在伽罗瓦域GF（2m）中系统地乘法两个任意场元素的电路。每个元素由m位二进制数表示。被乘数域元素串行地通过多个m-1模乘法器。来自每个m-1模乘法器的被乘数和乘积被传递通过形成部分乘积的乘法器场元素的位选通的网络。将部分乘积相加以形成最终产品的位表示。

5. 发明授权

US5590301A Address transformation in a cluster computer system 失效
标题翻译：群集计算机系统中的地址转换
公开(公告)号：US5590301A
公开(公告)日：1996-12-31
申请号：US540106
申请日：1995-10-06
申请人： Russell W. Guenthner , Leonard Rabins
发明人： Russell W. Guenthner , Leonard Rabins
IPC分类号： G06F15/16 , G06F9/46 , G06F12/02 , G06F12/06 , G06F12/08 , G06F9/26 , G06F9/34 , G06F12/00
CPC分类号： G06F12/0284 , G06F12/0811 , G06F12/084
摘要： In order to achieve the integration of a plurality of processors, each capable of directly addressing a limited internal space storage range, with a larger external memory space (e.g., a mass memory), the processors are organized into clusters, each having a plurality of processors and a common secondary cache. Each cluster is assigned a two-bit cluster number. Intermediate a primary cache in each processor and the secondary cache in the cluster, an address translator is provided for effecting transformation between internal memory space addresses and external memory space addresses. The external memory space is divided into areas private to each cluster and shared by all the processors. An internal address indicator bit, in conjunction with the cluster number from a requesting processor primary cache, is employed to set up the transformation either to the private external space of that cluster or the shared external space. In the reverse external-to-internal transformation, a pair of indicator bits are employed to set up the generation of an internal address and an indicator that the external address defines either shared external space or private external space for the designated cluster. A cluster member number assigned to each processor is used by the secondary cache of each cluster to track which processor sends/receives information to/from the mass memory.
摘要翻译：为了实现多个处理器的集成，每个处理器能够以更大的外部存储器空间（例如，大容量存储器）直接寻址有限的内部空间存储范围，将处理器组织成簇，每个处理器具有多个处理器和公共二级缓存。每个集群都分配了两位集群号。将每个处理器中的主缓存和集群中的二级缓存中间化，提供地址转换器，用于实现内部存储器空间地址和外部存储器空间地址之间的转换。外部存储器空间被划分为每个集群的私有区域并由所有处理器共享。内部地址指示符位与来自请求处理器主缓存的集群号一起被用于将转换建立到该集群的私有外部空间或共享的外部空间。在反向内部到内部的变换中，使用一对指示符位来建立内部地址的生成和外部地址定义共享的外部空间或指定集群的专用外部空间的指示符。分配给每个处理器的集群成员编号由每个集群的二级高速缓存使用，以跟踪哪个处理器向/从大容量存储器发送/接收信息。

6. 发明授权

US5367699A Central processing unit incorporation selectable, precisa ratio, speed of execution derating 失效
标题翻译：中央处理单元合并可选择，准确率，执行速度降额
公开(公告)号：US5367699A
公开(公告)日：1994-11-22
申请号：US800343
申请日：1991-11-26
申请人： Ronald E. Lange , Russell W. Guenthner , Leonard Rabins
发明人： Ronald E. Lange , Russell W. Guenthner , Leonard Rabins
IPC分类号： G06F9/30 , G06F9/38 , G06F7/62
CPC分类号： G06F9/3873 , G06F9/3836 , G06F9/3869
摘要： In order to obtain precise submodel control in a central processing unit, there is provided a subcounter which is controlled to count up from a beginning count as an instruction is executed and to count back down at the same rate to the reference count to obtain an effective delay before processing of the next instruction to be processed during normal program execution is started. Instruction transfer and decoding of the new instruction entering the pipeline is inhibited until the subcounter's most significant bit ("sign bit") changes state. If the subcounter is allowed to count during the entire count up and count down periods, a derated mode of 1/2 is achieved. To obtain other fractions, the subcounter is controlled to count periodically during one count direction period and to count full time during the other count direction period. In the exemplary embodiment, 1/4 and 3/4 derating is selectively achieved by the use of a modulo 3 counter which allows the subcounter to count only 1/3 the time in one or the other of the subcounter count up or count down periods.
摘要翻译：为了在中央处理单元中获得精确的子模型控制，提供了一个子计数器，其被控制为从执行指令开始计数开始计数，并以与参考计数相同的速率向下计数以获得有效的开始在正常程序执行期间处理下一个待处理指令之前的延迟。禁止进入管道的新指令的指令传输和解码，直到子计数器的最高有效位（“符号位”）改变状态。如果在整个计数和倒计时期间允许子计数器进行计数，则实现1/2的降额模式。为了获得其他分数，子计数器被控制以在一个计数方向期间周期性地计数，并且在另一个计数方向周期期间计数全时间。在示例性实施例中，通过使用模3计数器来选择性地实现1/4和3/4降额，所述模3计数器允许次计数器仅对次计数器的一个或另一个中的时间进行计数，。

7. 发明授权

US5276862A Safestore frame implementation in a central processor 失效
标题翻译：在中央处理器中实现Safestore框架
公开(公告)号：US5276862A
公开(公告)日：1994-01-04
申请号：US682801
申请日：1991-04-09
申请人： Lowell D. McCulley , Russell W. Guenthner , Clinton B. Eckard , Leonard Rabins , William A. Shelly , Ronald E. Lange , David S. Edwards
发明人： Lowell D. McCulley , Russell W. Guenthner , Clinton B. Eckard , Leonard Rabins , William A. Shelly , Ronald E. Lange , David S. Edwards
IPC分类号： G06F11/14 , G06F11/16 , G06F11/00
CPC分类号： G06F11/1441 , G06F11/1641 , G06F11/1637
摘要： In order to gather, store temporarily and deliver (if needed) central processor safestore information, a multiphase clock is employed to capture (one full clock cycle behind) the safestore information which typically includes all software visible registers in all (or selected) data manipulation chips of the CPU by routing the safestore information through temporary storage (under the influence of the multiphase clock) in a cache data array and into a special purpose XRAM module. Thus, upon the sensing of a fault, valid safestore information is available in the XRAM for analysis and, if appropriate, resumption of operation at a sequential point just previous to that at which the fault occurred.
摘要翻译：为了收集，存储和交付（如果需要的话）中央处理器保险箱信息，采用多相时钟来捕获（一个完整的时钟周期）保存存储信息，这些信息通常包括所有（或选定的）数据操作中的所有软件可见寄存器通过临时存储（在多相时钟的影响下）将缓存存储信息路由到高速缓存数据阵列中并进入特殊目的XRAM模块，从而使CPU的芯片。因此，在检测到故障时，XRAM中有效的保险箱信息可用于分析，如果适用，在刚刚发生故障的连续点恢复运行。

8. 发明授权

US5263034A Error detection in the basic processing unit of a VLSI central processor 失效
标题翻译： VLSI中央处理器的基本处理单元中的错误检测
公开(公告)号：US5263034A
公开(公告)日：1993-11-16
申请号：US594880
申请日：1990-10-09
申请人： Russell W. Guenthner , Clinton B. Eckard , Leonard Rabins , William A. Shelly , Ronald E. Lange , David S. Edwards , Bruce E. Flocken
发明人： Russell W. Guenthner , Clinton B. Eckard , Leonard Rabins , William A. Shelly , Ronald E. Lange , David S. Edwards , Bruce E. Flocken
IPC分类号： G06F11/16
CPC分类号： G06F11/1641
摘要： In order to provide efficient error detection in a central processor's Basic Processing Unit (BPU) including an AX (address and execution) module, a DN (decimal numeric) module and an FP (floating point) module, each module is provided redundantly in a master/slave pair, and the local result of data manipulation operations performed in each pair are compared for identity before the results are validated for subsequent use in the central processor.
摘要翻译：为了在包括AX（地址和执行）模块，DN（十进制数字）模块和FP（浮点））模块的中央处理器的基本处理单元（BPU）中提供有效的错误检测，每个模块在主/从对，并且将每个对中执行的数据操作操作的本地结果进行比较，以便在结果被验证以供后续在中央处理器中使用之前进行身份验证。

9. 发明授权

US4030067A Table lookup direct decoder for double-error correcting (DEC) BCH codes using a pair of syndromes 失效
标题翻译：用于使用一对综合征的双纠错（DEC）BCH码的表查找直接解码器
公开(公告)号：US4030067A
公开(公告)日：1977-06-14
申请号：US645056
申请日：1975-12-29
申请人： Thomas H. Howell , Gordon E. Gregg , Leonard Rabins
发明人： Thomas H. Howell , Gordon E. Gregg , Leonard Rabins
IPC分类号： G06F11/10 , G06F12/16 , H03M13/00 , H03M13/15 , G06F11/12
CPC分类号： G06F11/1012 , H03M13/15 , H03M13/152 , H03M13/1575
摘要： Apparatus for directly decoding and correcting double-bit random errors per word and for detecting triple-bit errors per word is disclosed. Said apparatus comprises a syndrome calculator which operates upon codewords received from memory and generates syndromes. The syndromes are operated upon and translated by a mapping device which generates pointers identifying the bits which are in error. The pointers are then passed through decoding means to generate error words which are summed with the received word from memory to provide a corrected codeword. The syndrome calculator may further provide a parity check signal to determine if a three-bit error is present, in which case the decoding means are not enabled and a signal is generated indicating that a triple-bit error has been detected which is not correctable.
摘要翻译：公开了用于每个字直接解码和校正双位随机错误并用于检测每字的三位错误的装置。所述装置包括对从存储器接收的码字进行操作的校正子计算器，并产生校正子。综合征由映射设备操作并转换，该映射设备产生标识错误位的指针。然后，指针通过解码装置产生与来自存储器的接收到的字相加的错误字，以提供校正的码字。校正子计算器还可以提供奇偶校验信号以确定是否存在三位错误，在这种情况下，解码装置不被使能，并且产生指示已经检测到不可校正的三位错误的信号。

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