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1. 发明授权

US06232184B1 Method of manufacturing floating gate of stacked-gate nonvolatile memory unit 有权
标题翻译：堆叠栅极非易失性存储器单元浮栅的制造方法
公开(公告)号：US06232184B1
公开(公告)日：2001-05-15
申请号：US09394270
申请日：1999-09-10
申请人： Ling-Sung Wang , Chingfu Lin
发明人： Ling-Sung Wang , Chingfu Lin
IPC分类号： H01L21336
CPC分类号： H01L21/28273
摘要： A method of manufacturing the floating gate of a stacked-gate type of nonvolatile memory unit. A gate oxide layer and a polysilicon layer are sequentially formed over a substrate. The polysilicon layer is etched to form a floating gate above the gate oxide layer. During the polysilicon etching operation, a polymeric material is also deposited on the sidewalls of the floating gate and over the exposed gate oxide. An isotropic chemical dry etching of the floating gate is carried out so that its bottom section is slightly wider than its top section. Finally, a thermal oxidation operation is carried out to form an oxide layer over the floating gate.
摘要翻译：一种制造堆叠栅极型非易失性存储器单元的浮置栅极的方法。栅极氧化层和多晶硅层依次形成在衬底上。蚀刻多晶硅层以在栅极氧化物层上方形成浮置栅极。在多晶硅蚀刻操作期间，聚合物材料也沉积在浮动栅极的侧壁上以及暴露的栅极氧化物上。执行浮动栅极的各向同性化学干蚀刻，使其底部部分比其顶部部分稍宽。最后，进行热氧化操作以在浮栅上形成氧化物层。

2. 发明授权

US06245667B1 Method of forming via 失效
标题翻译：形成通孔的方法
公开(公告)号：US06245667B1
公开(公告)日：2001-06-12
申请号：US09465905
申请日：1999-12-17
申请人： Ling-Sung Wang , Chingfu Lin , Chien-Jung Wang
发明人： Ling-Sung Wang , Chingfu Lin , Chien-Jung Wang
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a via. A stacked structure has a barrier layer and a metal line is formed over a substrate. Spacers capable of serving as a barrier are formed over tapering sidewalls of the stacked structure before vias and plugs are formed.
摘要翻译：形成通孔的方法。堆叠结构具有阻挡层，并且在衬底上形成金属线。在形成通孔和插塞之前，可以在堆叠结构的锥形侧壁上形成能够用作屏障的间隔物。

3. 发明授权

US08513143B2 Semiconductor structure and method of manufacturing 有权
标题翻译：半导体结构及制造方法
公开(公告)号：US08513143B2
公开(公告)日：2013-08-20
申请号：US13212469
申请日：2011-08-18
申请人： Mei-Hsuan Lin , Chih-Hsun Lin , Chih-Kang Chao , Ling-Sung Wang
发明人： Mei-Hsuan Lin , Chih-Hsun Lin , Chih-Kang Chao , Ling-Sung Wang
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L23/481 , H01L21/76802 , H01L21/76822 , H01L21/76825 , H01L21/76826 , H01L21/76832 , H01L21/76834 , H01L2924/0002 , H01L2924/00
摘要： The present application discloses a method of manufacturing a semiconductor structure. According to at least one embodiment, a first etch stop layer is formed over a conductive feature and a substrate, and the conductive feature is positioned over the substrate. A second etch stop layer is formed over the first etch stop layer. A first etch is performed to form an opening in the second etch stop layer, and the opening exposes a portion of the first etch stop layer. A second etch is performed to extend the opening downwardly by removing a portion of the exposed first etch stop layer, and the extended opening exposes a portion of the conductive feature.
摘要翻译：本申请公开了一种制造半导体结构的方法。根据至少一个实施例，在导电特征和衬底之上形成第一蚀刻停止层，并且导电特征位于衬底上。在第一蚀刻停止层上形成第二蚀刻停止层。执行第一蚀刻以在第二蚀刻停止层中形成开口，并且开口暴露第一蚀刻停止层的一部分。执行第二蚀刻以通过去除暴露的第一蚀刻停止层的一部分向下延伸开口，并且延伸的开口暴露导电特征的一部分。

4. 发明申请

US20130207166A1 Methods and Apparatus for Doped SiGe Source/Drain Stressor Deposition 有权
标题翻译：掺杂SiGe源/漏极应力沉积的方法和装置
公开(公告)号：US20130207166A1
公开(公告)日：2013-08-15
申请号：US13371177
申请日：2012-02-10
申请人： Chao-Hsuing Chen , Ling-Sung Wang , Chi-Yen Lin
发明人： Chao-Hsuing Chen , Ling-Sung Wang , Chi-Yen Lin
IPC分类号： H01L29/772 , H01L21/20
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/0257 , H01L21/02579 , H01L21/02639 , H01L29/0847 , H01L29/167 , H01L29/66628 , H01L29/66636
摘要： A semiconductor device system, structure and method of manufacture of a source/drain with SiGe stressor material to address effects due to dopant out-diffusion are disclosed. In an embodiment, a semiconductor substrate is provided with a gate structure, and recesses for source and drain are formed on opposing sides of the gate structure. Doped stressors are embedded into the recessed source and drain regions, and a plurality of layers of undoped stressor, lightly doped stressor, highly doped stressor, and a cap layer are formed in an in-situ epitaxial process. In another embodiment the doped stressor material is boron doped epitaxial SiGe. In an alternative embodiment an additional layer of undoped stressor material is formed.
摘要翻译：公开了一种利用SiGe应力材料制造源极/漏极的半导体器件系统，结构和方法，以解决由掺杂剂扩散引起的影响。在一个实施例中，半导体衬底设置有栅极结构，并且用于源极和漏极的凹槽形成在栅极结构的相对侧上。掺杂的应力源嵌入到凹陷的源极和漏极区域中，并且在原位外延工艺中形成多层未掺杂的应力源，轻掺杂应力源，高掺杂应力源和覆盖层。在另一个实施例中，掺杂应力源材料是硼掺杂的外延SiGe。在替代实施例中，形成附加的未掺杂应力源材料层。

5. 发明授权

US08468474B2 Reducing metal pits through optical proximity correction 有权
标题翻译：通过光学邻近校正减少金属凹坑
公开(公告)号：US08468474B2
公开(公告)日：2013-06-18
申请号：US13618045
申请日：2012-09-14
申请人： Jiun-Jie Huang , Chi-Yen Lin , Ling-Sung Wang
发明人： Jiun-Jie Huang , Chi-Yen Lin , Ling-Sung Wang
IPC分类号： G06F17/50
CPC分类号： H01L21/76838 , H01L23/528 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A method includes retrieving first layouts of an integrated circuit from a non-transitory computer-readable medium. The first layouts include a via pattern in a via layer, and a metal line pattern in a metal layer immediately over the via layer. The metal line pattern has an enclosure to the via pattern. The enclosure is increased to a second enclosure to generate second layouts of the integrated circuit.
摘要翻译：一种方法包括从非暂时计算机可读介质检索集成电路的第一布局。第一布局包括通孔层中的通孔图案，以及在通孔层上方的金属层中的金属线图案。金属线图案具有到通孔图案的外壳。外壳增加到第二个外壳以产生集成电路的第二布局。

6. 发明授权

US07473986B2 Positive-intrinsic-negative (PIN) diode semiconductor devices and fabrication methods thereof 有权
标题翻译：正本征负（PIN）二极管半导体器件及其制造方法
公开(公告)号：US07473986B2
公开(公告)日：2009-01-06
申请号：US11563814
申请日：2006-11-28
申请人： Kern-Huat Ang , Ling-Sung Wang
发明人： Kern-Huat Ang , Ling-Sung Wang
IPC分类号： H01L29/00
CPC分类号： H01L23/5252 , H01L27/1021 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and fabrication methods thereof. A first dielectric layer with a first conductor line along a first direction is disposed on a semiconductor substrate, wherein the top surface of the first conductor line is lower than the top surface of the first dielectric layer. A second dielectric layer comprising an opening corresponding to the first diode element is disposed on the first dielectric layer. A semiconductor diode component comprises a first diode element disposed on the first conductor line, wherein the top surface of the first diode element is level with the top surface of the first dielectric layer; and a second diode element and a third diode element are filled in the opening.
摘要翻译：半导体器件及其制造方法。具有沿着第一方向具有第一导体线的第一电介质层设置在半导体衬底上，其中第一导体线的顶表面比第一电介质层的顶表面低。包括对应于第一二极管元件的开口的第二电介质层设置在第一电介质层上。半导体二极管部件包括设置在第一导体线上的第一二极管元件，其中第一二极管元件的顶表面与第一介电层的顶表面平齐; 并且第二二极管元件和第三二极管元件填充在开口中。

7. 发明授权

US06524909B1 Self-aligned fabricating process and structure of source line of etox flash memory 有权
标题翻译：自动对准制造工艺和etox闪存源线结构
公开(公告)号：US06524909B1
公开(公告)日：2003-02-25
申请号：US09494524
申请日：2000-01-31
申请人： Ling-Sung Wang , Jyh-Ren Wu
发明人： Ling-Sung Wang , Jyh-Ren Wu
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/28273
摘要： A self-aligned fabricating process and a structure of ETOX flash memory. A plurality of parallel lines for device isolation is formed in a substrate, and then forming a plurality of parallel stacked gates above the substrate. The device isolation lines and the stacked gates are perpendicular to each other. A plurality of first insulation layers is formed such that an insulation layer is formed over each stacked gate. Spacers are also formed over the sidewalls of each stacked gate. A plurality of source arrays and drain arrays are formed in the substrate between neighboring stacked gates. The source and drain arrays are parallel to the stacked gates, with a source array and a drain array formed in alternating positions between the stacked gates. Each source array comprises a plurality of source-doped regions located between the device isolation lines respectively. Similarly, each drain array has a plurality of drain-doped regions located between the device isolation lines. A plurality of source lines is formed in the space between neighboring spacers above the source array.
摘要翻译：自对准制造工艺和ETOX闪存的结构。在衬底中形成用于器件隔离的多条平行线，然后在衬底上形成多个平行的堆叠栅极。器件隔离线和堆叠栅极彼此垂直。形成多个第一绝缘层，使得在每个堆叠的栅极上形成绝缘层。隔板也形成在每个堆叠门的侧壁上。在相邻堆叠栅极之间的衬底中形成多个源极阵列和漏极阵列。源极和漏极阵列平行于堆叠栅极，源极阵列和漏极阵列形成在堆叠栅极之间的交替位置。每个源极阵列分别包括位于器件隔离线之间的多个源极掺杂区域。类似地，每个漏极阵列具有位于器件隔离线之间的多个漏极掺杂区域。在源阵列上方的相邻间隔物之间的空间中形成多条源极线。

8. 发明授权

US6146946A Method of fabricating a flash memory 有权
标题翻译：制造闪速存储器的方法
公开(公告)号：US6146946A
公开(公告)日：2000-11-14
申请号：US417393
申请日：1999-10-13
申请人： Ling-Sung Wang , Jyh-Ren Wu
发明人： Ling-Sung Wang , Jyh-Ren Wu
IPC分类号： H01L21/28 , H01L29/423 , H01L29/51 , H01L21/336
CPC分类号： H01L29/511 , H01L21/28273 , H01L29/42324
摘要： The invention describes a method of fabricating an integrated circuit used to prevent undercutting of an oxide layer due to wet etching. A semiconductor substrate has a gate formed thereon. A conformal oxide layer is formed to cover the gate. Then, a nitrogen ion implantation process is performed to introduce nitrogen ions into the surface of the conformal oxide layer. A high temperature thermal oxidation is performed in order to form Si--N bonds, that is, the nitrogen ions bonding with the silicon atoms of the conformal oxide layer, or to form Si--ON bonds, that is, the nitrogen ions bonding with the oxygen atoms of the conformal oxide layer. A dielectric layer, which covers the conformal oxide layer, is formed. Thereafter, the dielectric layer is etched back to form spacers on the sidewalls of the gate. A wet etching process is performed to remove a part of the conformal oxide layer exposed by the spacers.
摘要翻译：本发明描述了一种制造集成电路的方法，该集成电路用于防止由于湿蚀刻而导致的氧化层的底切。半导体衬底具有形成在其上的栅极。形成保形氧化物层以覆盖栅极。然后，进行氮离子注入工艺以将氮离子引入保形氧化物层的表面。进行高温热氧化以形成Si-N键，即与保形氧化物层的硅原子结合的氮离子，或者形成Si-ON键，即氮离子与保形氧化物层的氧原子。形成覆盖保形氧化物层的电介质层。此后，电介质层被回蚀以在栅极的侧壁上形成间隔物。执行湿蚀刻工艺以去除由间隔物暴露的一部分共形氧化物层。

9. 发明授权

US6026028A Hot carrier injection programming and negative gate voltage channel erase flash EEPROM structure 失效
标题翻译：热载波注入编程和负栅极电压通道擦除闪存EEPROM结构
公开(公告)号：US6026028A
公开(公告)日：2000-02-15
申请号：US123305
申请日：1998-07-28
申请人： Chen-Hsi Lin , Chih-Ming Chen , Ling-Sung Wang , Horng-Ming Lee , Ko-Hsing Chang
发明人： Chen-Hsi Lin , Chih-Ming Chen , Ling-Sung Wang , Horng-Ming Lee , Ko-Hsing Chang
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C13/00
CPC分类号： H01L29/7885
摘要： A flash electrical erasable programmable read only memory structure that utilizes hot carrier injection for programming and negative gate voltage to carry out channel erase operations. Characteristic of the memory structure includes a triple well structure having a P-well and an N-well located within a P-type substrate, wherein the N-well isolated the P-well from the P-type substrate. Therefore, an independently isolated triple well structure is established during memory erase operation.
摘要翻译：闪存电可擦除可编程只读存储器结构，其利用热载流子注入用于编程和负栅极电压来执行通道擦除操作。存储器结构的特征包括具有P阱和位于P型衬底内的N阱的三阱结构，其中N阱从P型衬底隔离P阱。因此，在存储器擦除操作期间建立独立隔离的三重阱结构。

10. 发明授权

US09343318B2 Salicide formation using a cap layer 有权
标题翻译：使用盖层的自杀剂形成
公开(公告)号：US09343318B2
公开(公告)日：2016-05-17
申请号：US13367989
申请日：2012-02-07
申请人： Mei-Hsuan Lin , Chih-Hsun Lin , Ching-Hua Chu , Ling-Sung Wang
发明人： Mei-Hsuan Lin , Chih-Hsun Lin , Ching-Hua Chu , Ling-Sung Wang
IPC分类号： H01L21/285 , H01L29/417 , H01L29/66 , H01L29/78
CPC分类号： H01L21/28518 , H01L21/02381 , H01L21/02425 , H01L21/02532 , H01L21/02617 , H01L21/0262 , H01L21/02631 , H01L21/28052 , H01L21/28097 , H01L21/2855 , H01L21/28556 , H01L21/28568 , H01L29/41783 , H01L29/4933 , H01L29/4975 , H01L29/665 , H01L29/66507 , H01L29/7845 , H01L29/7848
摘要： A semiconductor device having a source feature and a drain feature formed in a substrate. The semiconductor device having a gate stack over a portion of the source feature and over a portion of the drain feature. The semiconductor device further having a first cap layer formed over substantially the entire source feature not covered by the gate stack, and a second cap layer formed over substantially the entire drain feature not covered by the gate stack. A method of forming a semiconductor device including forming a source feature and drain feature in a substrate. The method further includes forming a gate stack over a portion of the source feature and over a portion of the drain feature. The method further includes depositing a first cap layer over substantially the entire source feature not covered by the gate stack and a second cap layer over substantially the entire drain feature not covered by the gate stack.
摘要翻译：一种半导体器件，其具有形成在衬底中的源特征和漏极特征。该半导体器件在源特征的一部分上方并且在漏极特征的一部分上方具有栅极堆叠。所述半导体器件还具有形成在基本上整个源极特征上的第一覆盖层，其未被所述栅极堆叠覆盖，以及形成在基本上整个漏极特征（未被所述栅极堆叠覆盖）的第二覆盖层。一种形成半导体器件的方法，包括在衬底中形成源极特征和漏极特征。该方法还包括在源特征的一部分上并在漏极特征的一部分之上形成栅叠层。该方法还包括在未被栅极堆叠覆盖的基本上整个源特征上沉积第一盖层，以及在未被栅极堆叠覆盖的基本整个漏极特征上沉积第二盖层。

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