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    • 3. 发明授权
    • Gate configuration for nanowire electronic devices
    • 纳米线电子器件的栅极配置
    • US07473943B2
    • 2009-01-06
    • US11233398
    • 2005-09-22
    • Shahriar MostarshedJian ChenFrancisco LeonYaoling PanLinda T. Romano
    • Shahriar MostarshedJian ChenFrancisco LeonYaoling PanLinda T. Romano
    • H01L29/80
    • H01L29/0665B82Y10/00H01L29/0673H01L29/42384H01L29/42392H01L29/775H01L29/785H01L29/78645H01L29/78681H01L29/7869Y10S977/762Y10S977/932Y10S977/938
    • Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.
    • 描述了具有改进的门结构的电子设备的方法,系统和装置。 电子装置包括至少一个纳米线。 栅极接触沿至少一个纳米线的长度的至少一部分定位。 介电材料层在栅极接触和至少一个纳米线之间。 源极触点和漏极触点与至少一个纳米线接触。 源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。 另一方面,一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。 环形第一栅极区域沿着纳米线长度的一部分包围纳米线。 第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。 源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。