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1. 发明授权

US6133155A Method for preventing corrosion of a metallic layer of a semiconductor chip 有权
标题翻译：防止半导体芯片的金属层腐蚀的方法
公开(公告)号：US6133155A
公开(公告)日：2000-10-17
申请号：US198308
申请日：1998-11-23
申请人： Lin Tsai-Sen , Chou-Shin Jou , Tings Wang , Chin-Kang Li
发明人： Lin Tsai-Sen , Chou-Shin Jou , Tings Wang , Chin-Kang Li
IPC分类号： G03F7/42 , H01L21/02 , H01L21/3213 , H01L21/3065
CPC分类号： H01L21/02071 , G03F7/42 , G03F7/427
摘要： The present invention provides a method for preventing corrosion of an aluminum-containing metallic layer having a plurality of trenches on the surface of a semiconductor chip caused by chlorine atoms residing on side walls of the trenches of the metallic layer after a trench etching process. The method comprises the following steps: (1) removing the photo resistance layer on top of the metallic layer by ashing at temperatures between 178.degree. C. and 200.degree. C. after a trench etching process, (2) using an acidic solution comprising hydroxylamine (NH.sub.2 OH), hydroquinone C.sub.6 H.sub.4 (OH).sub.2, monoethanolanine (HOCH.sub.2 CH.sub.2 NH.sub.2) and water to wash off residues on the surface of the semiconductor chip, and (3) heating the semiconductor chip for a predetermined time period at temperatures between 200.degree. C. and 250.degree. C. so as to completely dissipate the chlorine atoms resided on the side walls of the metallic layer for preventing recurrent corrosion of an aluminum-containing metallic layer.
摘要翻译：本发明提供了一种在沟槽蚀刻工艺之后，由位于金属层的沟槽的侧壁上的氯原子引起的在半导体芯片的表面上具有多个沟槽的含铝金属层的腐蚀的方法。该方法包括以下步骤：（1）在沟槽蚀刻工艺之后，在178℃至200℃之间的温度下，通过灰化除去金属层顶部的光电层，（2）使用包含羟胺的酸性溶液（NH 2 OH），氢醌C 6 H 4（OH）2，单乙醇化（HOCH 2 CH 2 NH 2）和水，以清洗半导体芯片表面上的残留物，和（3）在200℃至200℃的温度下加热半导体芯片预定时间 250℃，以便完全消散存在于金属层的侧壁上的氯原子，以防止含铝金属层的反复腐蚀。

2. 发明授权

US06492188B1 Monitor method for quality of metal ARC (antireflection coating) layer 有权
标题翻译：金属ARC（防反射涂层）质量监测方法
公开(公告)号：US06492188B1
公开(公告)日：2002-12-10
申请号：US09265962
申请日：1999-03-11
申请人： Tsai-Sen Lin , Bor-Shiun Wu , Chou-Shin Jou , Tings Wang
发明人： Tsai-Sen Lin , Bor-Shiun Wu , Chou-Shin Jou , Tings Wang
IPC分类号： G01R3126
CPC分类号： H01L22/24
摘要： The present invention relates to a monitor method for quality of metal Antireflection Coating (ARC) layer and, more particularly, to a fast and accurate monitor method for quality of metal ARC layer. By using of immersing a silicon wafer comprising an ARC layer into an acidic (such as a developer) or an alkalescent solution for about 200-300 seconds, according to the present invention, at weak points of the metal ARC layer there occur voids (defects) due to a Galvanic cell effect enhanced by these chemical solutions and then how many defects can be counted by a wafer defect inspector such as a KLA instrument so that quality of the metal ARC layer can be monitored by this defect number. Besides, Since the silicon wafer used as a sample for the wafer defect inspector simply comes from a production line, i.e. a developing process, rather than from other additional processing, said method allows for fast and accurately monitoring quality of the metal ARC layers.
摘要翻译：金属防反射涂层（ARC）层的质量监测方法技术领域本发明涉及金属防反射涂层（ARC）层的质量监测方法，更具体地说，涉及金属ARC层质量的快速准确的监测方法。通过根据本发明，将包含ARC层的硅晶片浸入酸性（例如显影剂）或碱性溶液中约200-300秒，在金属ARC层的弱点处发生空隙（缺陷）由于这些化学溶液增强的电化学电池效应，然后可以通过诸如KLA仪器的晶片缺陷检查器计数多少个缺陷，以便可以通过该缺陷数来监测金属ARC层的质量。此外，由于用作晶片缺陷检查器的样品的硅晶片简单地来自生产线，即显影过程，而不是来自其他附加处理，所述方法允许快速且准确地监测金属ARC层的质量。

3. 发明授权

US06417099B1 Method for controlling dopant diffusion in a plug-shaped doped polysilicon layer on a semiconductor wafer 有权
标题翻译：用于控制半导体晶片上的塞状掺杂多晶硅层中的掺杂剂扩散的方法
公开(公告)号：US06417099B1
公开(公告)日：2002-07-09
申请号：US09148050
申请日：1998-09-03
申请人： Chung-Shih Tsai , Der-Tgyr Fan , Chou-Shin Jou , Tings Wang
发明人： Chung-Shih Tsai , Der-Tgyr Fan , Chou-Shin Jou , Tings Wang
IPC分类号： H07L2128
CPC分类号： H01L21/76877 , H01L21/28525
摘要： The present invention provides a method for controlling dopant density of a plug-shaped doped polysilicon layer formed within a plug-shaped recess to prevent the dopant contained in the plug-shaped doped polysilicon layer from diffusing into a conductive layer under the plug-shaped recess through a bottom side of the plug-shaped recess, the plug-shaped recess being formed within a dielectric layer which is positioned above the conductive layer, the method comprising: (1) forming an undoped silicon layer on the surface of the plug-shaped recess; (2) forming a doped polysilicon layer on top of the undoped silicon layer to fill the plug-shaped recess; and (3) performing a thermal treatment to the semiconductor wafer so as to make the doped poly-silicon layer interact with the undoped silicon layer inside the plug-shaped recess which forms a completely doped polysilicon layer within the plug-shaped recess.
摘要翻译：本发明提供了一种用于控制形成在插塞状凹部内的插塞状掺杂多晶硅层的掺杂剂密度的方法，以防止包含在插塞状掺杂多晶硅层中的掺杂剂扩散到插塞形凹部下方的导电层通过插塞形凹部的底侧，插塞形凹槽形成在位于导电层上方的电介质层内，该方法包括：（1）在插塞形状的表面上形成未掺杂的硅层休息（2）在未掺杂的硅层的顶部上形成掺杂多晶硅层以填充插塞状凹部; 和（3）对所述半导体晶片进行热处理，以使所述掺杂多晶硅层与在所述插塞形凹部内形成完全掺杂多晶硅层的所述插塞形凹槽内的未掺杂硅层相互作用。

4. 发明授权

US06365064B1 Method for evenly immersing a wafer in a solution 失效
标题翻译：将晶片均匀浸入溶液中的方法
公开(公告)号：US06365064B1
公开(公告)日：2002-04-02
申请号：US09198307
申请日：1998-11-23
申请人： Chung-Shih Tsai , Chou-Shin Jou , Der-Tsyr Fan
发明人： Chung-Shih Tsai , Chou-Shin Jou , Der-Tsyr Fan
IPC分类号： H01L2100
CPC分类号： H01L21/67086 , H01L21/67057
摘要： The present invention provides a method for evenly immersing a wafer in a solution held in a solution chamber, which comprises the following steps: (1) placing at least one disk-shaped wafer inside a wafer holder which is used for vertically holding at least one wafer, (2) immersing the wafer holder into the solution vertically so that each wafer in the wafer holder can be vertically immersed into and react with the solution, (3) vertically rotating the wafer holder in the solution so as to invert each wafer in the wafer holder upside down, and (4) removing the wafer holder from the solution vertically after immersing the wafer in the solution for a predetermined period of time.
摘要翻译：本发明提供一种将晶片均匀地浸入保持在溶液室中的溶液的方法，其包括以下步骤：（1）将至少一个盘状晶片放置在用于垂直保持至少一个（2）将晶片保持器垂直浸入溶液中，使得晶片保持器中的每个晶片可以垂直浸入溶液中并与溶液反应，（3）将晶片保持器在溶液中垂直旋转，从而将每个晶片反转晶片保持器倒置，并且（4）在将晶片浸入溶液中一段预定的时间后，垂直移除晶片固定器。

5. 发明授权

US06677216B2 Method of making IC capacitor 失效
标题翻译：制造IC电容的方法
公开(公告)号：US06677216B2
公开(公告)日：2004-01-13
申请号：US10263397
申请日：2002-10-01
申请人： Chun-Pey Cho , Tsai-Sen Lin , Chou-Shin Jou , Chuan-Yi Wang , Jen-Chieh Chang , Yi-Fu Chung , Huei-Ping Hsieh
发明人： Chun-Pey Cho , Tsai-Sen Lin , Chou-Shin Jou , Chuan-Yi Wang , Jen-Chieh Chang , Yi-Fu Chung , Huei-Ping Hsieh
IPC分类号： H01L2120
CPC分类号： H01L28/60 , H01L21/28518 , Y10S438/952
摘要： Embodiments of the present invention relate to a method of making an IC capacitor. In one embodiment, the method comprises providing a substrate, forming a polycide layer on the substrate, and forming an insulating amorphous silicon layer on the polycide layer. The insulating amorphous silicon layer serves as an anti-reflection layer. The method further comprises implanting n-type ions into the insulating amorphous silicon layer to transform the insulating amorphous silicon layer into a conductive amorphous silicon layer, and patterning the polycide layer and the conductive amorphous silicon layer to form a bottom electrode on the substrate. A dielectric layer is formed on the bottom electrode and the substrate, and a conductor layer is formed on the dielectric layer. The conductor layer is patterned to form a top electrode on the dielectric layer.
摘要翻译：本发明的实施例涉及一种制造IC电容器的方法。在一个实施例中，该方法包括提供衬底，在衬底上形成多晶硅化物层，并在多晶硅化物层上形成绝缘非晶硅层。绝缘非晶硅层用作防反射层。该方法还包括将n型离子注入到绝缘非晶硅层中以将绝缘非晶硅层转变为导电非晶硅层，以及图案化多晶硅化物层和导电非晶硅层，以在衬底上形成底部电极。在底部电极和基板上形成电介质层，在电介质层上形成导体层。将导体层图案化以在电介质层上形成顶部电极。

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