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    • 1. 发明授权
    • Architecture for joint detection hardware accelerator
    • 联合检测硬件加速器架构
    • US07953958B2
    • 2011-05-31
    • US11818055
    • 2007-06-12
    • John Zijun ShenPaul D. KrivacekThomas J. Barber, Jr.Lidwine MartinotAiguo YanMarko Kocic
    • John Zijun ShenPaul D. KrivacekThomas J. Barber, Jr.Lidwine MartinotAiguo YanMarko Kocic
    • G06F15/76G06F9/302
    • H04B1/7105H04B2201/70707H04B2201/70711
    • A joint detection system is configured to perform joint detection of received signals and includes a joint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and output data values; one or more computation units to process the input data values and the intermediate results, and to provide output data values to the memory unit; a controller to control the memory and the one or more computation units to perform joint detection processing; and an external interface to receive the input data values from the host processor and to provide output data values to the host processor. The computation units may include a complex multiply accumulate unit, a simplified complex multiply accumulate unit and a normalized floating point divider. The memory unit may include an input memory, a matrix memory, a main memory and an output memory.
    • 联合检测系统被配置为执行接收信号的联合检测,并且包括联合检测加速器和主机处理器。 联合检测加速器可以包括用于存储输入数据值,中间结果和输出数据值的存储单元; 一个或多个计算单元,用于处理输入数据值和中间结果,并向存储器单元提供输出数据值; 控制器,用于控制存储器和一个或多个计算单元进行联合检测处理; 以及用于从主处理器接收输入数据值并向主机处理器提供输出数据值的外部接口。 计算单元可以包括复数乘法单元,简化复乘法累积单元和归一化浮点除法器。 存储器单元可以包括输入存储器,矩阵存储器,主存储器和输出存储器。
    • 2. 发明授权
    • Method and apparatus for joint detection
    • 联合检测方法和装置
    • US07916841B2
    • 2011-03-29
    • US11545857
    • 2006-10-11
    • Aiguo YanLidwine MartinotMarko KocicPaul D. KrivacekThomas J. Barber, Jr.John Zijun Shen
    • Aiguo YanLidwine MartinotMarko KocicPaul D. KrivacekThomas J. Barber, Jr.John Zijun Shen
    • H04M1/64H04L25/49
    • H04B1/7105H04B2201/70711
    • A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals and includes a joint detector accelerator and a programmable digital signal processor (DSP). The joint detector accelerator is configured to perform front-end processing of first data inputted to the joint detector accelerator and output second data resulting from the front-end processing. The joint detector accelerator is further configured to perform back-end processing using at least third data inputted to the joint detector accelerator. The programmable DSP is coupled to the joint detector accelerator, and the programmable DSP is programmed to perform at least one intermediate processing operation using the second data outputted by the joint detector accelerator. The programmable DSP is further programmed to output the third data resulting from the intermediate processing operation to the joint detector accelerator.
    • 提供联合检测系统及相关方法。 联合检测系统被配置为执行接收信号的联合检测,并且包括联合检测器加速器和可编程数字信号处理器(DSP)。 联合检测器加速器被配置为执行输入到联合检测器加速器的第一数据的前端处理,并输出从前端处理得到的第二数据。 联合检测器加速器还被配置为使用输入到联合检测器加速器的至少第三数据来执行后端处理。 可编程DSP耦合到联合检测器加速器,并且可编程DSP被编程为使用由联合检测器加速器输出的第二数据执行至少一个中间处理操作。 可编程DSP进一步编程为将由中间处理操作产生的第三数据输出到联合检测器加速器。
    • 3. 发明授权
    • Fixed-point implementation of a joint detector
    • 联合检测器的定点实现
    • US07949925B2
    • 2011-05-24
    • US11546062
    • 2006-10-11
    • Lidwine MartinotAiguo YanMarko KocicThomas J. Barber, Jr.John Zijun Shen
    • Lidwine MartinotAiguo YanMarko KocicThomas J. Barber, Jr.John Zijun Shen
    • H03M13/00
    • H04B1/7105H04B2201/70707H04L25/0224
    • A joint detection system and associated methods are provided. A joint detection system is configured to perform joint detection of received signals. The joint detection system includes a joint detector accelerator configured to perform an operation of the joint detection of the received signals, wherein the joint detection includes computing joint detection variables. The operation includes a multiply and accumulate operation resulting in a value in an accumulator, and the value in the accumulator includes a plurality of bits. The joint detector accelerator is configured to select a subset of bits of the plurality of bits of the value in the accumulator, where the subset of bits selected is configurable. The joint detector accelerator is further configured to store the subset of bits into a memory as a fixed point representation.
    • 提供联合检测系统及相关方法。 联合检测系统被配置为执行接收信号的联合检测。 联合检测系统包括联合检测器加速器,其被配置为执行对接收信号的联合检测的操作,其中联合检测包括计算关节检测变量。 该操作包括产生累加器中的值的乘法和累加运算,累加器中的值包括多个位。 联合检测器加速器被配置为选择累加器中的值的多个比特的子集,其中选择的比特的子集是可配置的。 联合检测器加速器还被配置为将位的子集存储到存储器中作为固定点表示。
    • 5. 发明申请
    • Architecture for joint detection hardware accelerator
    • 联合检测硬件加速器架构
    • US20080080468A1
    • 2008-04-03
    • US11818055
    • 2007-06-12
    • John Zijun ShenPaul D. KrivacekThomas J. BarberLidwine MartinotAiguo YanMarko Kocic
    • John Zijun ShenPaul D. KrivacekThomas J. BarberLidwine MartinotAiguo YanMarko Kocic
    • H04B7/216
    • H04B1/7105H04B2201/70707H04B2201/70711
    • A joint detection system is configured to perform joint detection of received signals and includes ajoint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and output data values; one or more computation units to process the input data values and the intermediate results, and to provide output data values to the memory unit; a controller to control the memory and the one or more computation units to perform joint detection processing; and an external interface to receive the input data values from the host processor and to provide output data values to the host processor. The computation units may include a complex multiply accumulate unit, a simplified complex multiply accumulate unit and a normalized floating point divider. The memory unit may include an input memory, a matrix memory, a main memory and an output memory.
    • 联合检测系统被配置为执行接收信号的联合检测,并且包括联合检测加速器和主机处理器。 联合检测加速器可以包括用于存储输入数据值,中间结果和输出数据值的存储单元; 一个或多个计算单元,用于处理输入数据值和中间结果,并向存储器单元提供输出数据值; 控制器,用于控制存储器和一个或多个计算单元进行联合检测处理; 以及用于从主处理器接收输入数据值并向主机处理器提供输出数据值的外部接口。 计算单元可以包括复数乘法单元,简化复乘法累积单元和归一化浮点除法器。 存储器单元可以包括输入存储器,矩阵存储器,主存储器和输出存储器。
    • 6. 发明申请
    • Fixed-point implementation of a joint detector
    • 联合检测器的定点实现
    • US20080089448A1
    • 2008-04-17
    • US11546062
    • 2006-10-11
    • Lidwine MartinotAiguo YanMarko KocicThomas J. BarberJohn Zijun Shen
    • Lidwine MartinotAiguo YanMarko KocicThomas J. BarberJohn Zijun Shen
    • H04L27/06
    • H04B1/7105H04B2201/70707H04L25/0224
    • A joint detection system and associated methods are provided. A joint detection system is configured to perform joint detection of received signals. The joint detection system includes a joint detector accelerator configured to perform an operation of the joint detection of the received signals, wherein the joint detection includes computing joint detection variables. The operation includes a multiply and accumulate operation resulting in a value in an accumulator, and the value in the accumulator includes a plurality of bits. The joint detector accelerator is configured to select a subset of bits of the plurality of bits of the value in the accumulator, where the subset of bits selected is configurable. The joint detector accelerator is further configured to store the subset of bits into a memory as a fixed point representation.
    • 提供联合检测系统及相关方法。 联合检测系统被配置为执行接收信号的联合检测。 联合检测系统包括联合检测器加速器,其被配置为执行对接收信号的联合检测的操作,其中联合检测包括计算关节检测变量。 该操作包括产生累加器中的值的乘法和累加运算,累加器中的值包括多个位。 联合检测器加速器被配置为选择累加器中的值的多个比特的子集,其中选择的比特的子集是可配置的。 联合检测器加速器还被配置为将位的子集存储到存储器中作为固定点表示。
    • 8. 发明申请
    • Method and apparatus for joint detection
    • 联合检测方法和装置
    • US20080080638A1
    • 2008-04-03
    • US11545857
    • 2006-10-11
    • Aiguo YanLidwine MartinotMarko KocicPaul D. KrivacekThomas J. BarberJohn Zijun Shen
    • Aiguo YanLidwine MartinotMarko KocicPaul D. KrivacekThomas J. BarberJohn Zijun Shen
    • H04L25/49
    • H04B1/7105H04B2201/70711
    • A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals and includes a joint detector accelerator and a programmable digital signal processor (DSP). The joint detector accelerator is configured to perform front-end processing of first data inputted to the joint detector accelerator and output second data resulting from the front-end processing. The joint detector accelerator is further configured to perform back-end processing using at least third data inputted to the joint detector accelerator. The programmable DSP is coupled to the joint detector accelerator, and the programmable DSP is programmed to perform at least one intermediate processing operation using the second data outputted by the joint detector accelerator. The programmable DSP is further programmed to output the third data resulting from the intermediate processing operation to the joint detector accelerator.
    • 提供联合检测系统及相关方法。 联合检测系统被配置为执行接收信号的联合检测,并且包括联合检测器加速器和可编程数字信号处理器(DSP)。 联合检测器加速器被配置为执行输入到联合检测器加速器的第一数据的前端处理,并输出从前端处理得到的第二数据。 联合检测器加速器还被配置为使用输入到联合检测器加速器的至少第三数据来执行后端处理。 可编程DSP耦合到联合检测器加速器,并且可编程DSP被编程为使用由联合检测器加速器输出的第二数据执行至少一个中间处理操作。 可编程DSP进一步编程为将由中间处理操作产生的第三数据输出到联合检测器加速器。