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1. 发明申请

US20110208071A1 SMART NON-INVASIVE ARRAY-BASED HEMODYNAMIC MONITORING SYSTEM on CHIP AND METHOD THEREOF 审中-公开
标题翻译：基于智能非基于阵列的HEMODYMM监测系统及其方法
公开(公告)号：US20110208071A1
公开(公告)日：2011-08-25
申请号：US13034011
申请日：2011-02-24
申请人： Liang-Hung Lu , Wei-Cheng Tian , Shao-Yi Chien , Jiun-Lang Huang , Po-Ling Kuo , Ping-Cheng Yeh
发明人： Liang-Hung Lu , Wei-Cheng Tian , Shao-Yi Chien , Jiun-Lang Huang , Po-Ling Kuo , Ping-Cheng Yeh
IPC分类号： A61B5/02
CPC分类号： A61B5/0285 , A61B5/02125 , A61B5/6822 , A61B2562/0247 , A61B2562/028 , A61B2562/046
摘要： A non-invasive array-based hemodynamic monitoring system on chip is disclosed. The non-invasive array-based hemodynamic monitoring system on chip comprises a CMOS MEMS pressure sensor array, a readout circuit, and a signal control system. The CMOS MEMS pressure sensor array is configured to sense a pulse wave of a blood vessel. The readout circuit is coupled with each of the CMOS compatible MEMS pressure sensors and is configured to read the pulse wave and transformed the pulse wave into a voltage signal. The signal control system is coupled with each of the readout circuit, and is configured to estimate a wave velocity according to the voltage signal.
摘要翻译：公开了一种基于非侵入式阵列的血液动力学监测系统。基于非侵入式阵列的血液动力学监测系统包括CMOS MEMS压力传感器阵列，读出电路和信号控制系统。 CMOS MEMS压力传感器阵列被配置为感测血管的脉搏波。读出电路与每个CMOS兼容的MEMS压力传感器耦合，并且被配置为读取脉搏波并将脉冲波变换成电压信号。信号控制系统与每个读出电路耦合，并且被配置为根据电压信号估计波速。

2. 发明授权

US07948482B2 Apparatus for testing driving circuit for display 有权
标题翻译：用于测试显示驱动电路的装置
公开(公告)号：US07948482B2
公开(公告)日：2011-05-24
申请号：US11942444
申请日：2007-11-19
申请人： Chuan-Che Lee , Jiun-Lang Huang , Jui-Jer Huang
发明人： Chuan-Che Lee , Jiun-Lang Huang , Jui-Jer Huang
IPC分类号： G06F3/038 , G09G5/00
CPC分类号： H03M1/56 , G09G3/006 , G09G2310/027 , H03M1/109 , Y10S345/904
摘要： An apparatus for testing a driving circuit for a display is disclosed. The apparatus includes a selecting circuit, a reference voltage generator and an analog-to-digital converter (ADC). The selecting circuit includes many input terminals and an output terminal. The input terminals are respectively coupled to many output pins of the driving circuit, while the selecting circuit is used for selecting one of the output pins to electrically connect the output terminal of the selecting circuit. The reference voltage generator is coupled to at least one of the output pins for generating a reference voltage. The ADC is coupled to the output terminal of the selecting circuit for outputting a digital value based on a difference between an output voltage outputted from the output terminal of the selecting circuit and the reference voltage produced by the reference voltage generator.
摘要翻译：公开了一种用于测试显示器的驱动电路的装置。该装置包括选择电路，参考电压发生器和模数转换器（ADC）。选择电路包括许多输入端子和输出端子。输入端子分别耦合到驱动电路的许多输出引脚，而选择电路用于选择输出引脚之一以电连接选择电路的输出端。参考电压发生器耦合到至少一个输出引脚，用于产生参考电压。 ADC耦合到选择电路的输出端，用于基于从选择电路的输出端输出的输出电压与由参考电压发生器产生的参考电压之差来输出数字值。

3. 发明申请

US20130127647A1 SUCCESSIVE APPROXIMATION REGISTER ADC AND METHOD OF LINEARITY CALIBRATION THEREIN 有权
标题翻译：随机逼近寄存器ADC及其线性校准方法
公开(公告)号：US20130127647A1
公开(公告)日：2013-05-23
申请号：US13343725
申请日：2012-01-05
申请人： Xuan-Lun Huang , Jiun-Lang Huang
发明人： Xuan-Lun Huang , Jiun-Lang Huang
IPC分类号： H03M1/10 , H03M1/38
CPC分类号： H03M1/1061 , H03M1/468
摘要： A successive approximation register analog to digital converter (SAR ADC) and a method of linearity calibration therein are provided. Each composed element Ei in a part of the composed elements includes a main constructed element Ei0 and wi sub constructed element Ei1, Ei2, . . . , Eiwi. The SAR ADC selects a part of the sub constructed elements Ei1, Ei2, . . . , Eiwi and make them non-functional when a missing decision level is caused by the composed element Ei. An overlap cancellation to the obtained missing code numbers is performed, compensation coefficients are updated according to the missing code numbers after the overlap cancellation, and a compensation to the corresponding digital value is performed according to the compensation coefficients. The present disclosure prevents the necessity of matching each composed element of the DAC in the SAR ADC.
摘要翻译：提供逐次逼近寄存器模数转换器（SAR ADC）及其线性校准方法。组成元件的一部分中的每个组成元素Ei包括主构造元素Ei0和wi子构造元素Ei1，Ei2。。。 i i SAR ADC选择子构造元素Ei1，Ei2的一部分。。。，Eiwi，并且当组合元素Ei导致丢失的决策级别时，它们不起作用。执行对所获得的丢失码号的重叠取消，根据重叠消除之后的丢失码号来更新补偿系数，并根据补偿系数对相应的数字值进行补偿。本公开防止在SAR ADC中匹配DAC的每个组成元件的必要性。

4. 发明授权

US08487794B2 Successive approximation register ADC and method of linearity calibration therein 有权
标题翻译：逐次逼近寄存器ADC及其线性校准方法
公开(公告)号：US08487794B2
公开(公告)日：2013-07-16
申请号：US13343725
申请日：2012-01-05
申请人： Xuan-Lun Huang , Jiun-Lang Huang
发明人： Xuan-Lun Huang , Jiun-Lang Huang
IPC分类号： H03M1/10
CPC分类号： H03M1/1061 , H03M1/468
摘要： A successive approximation register analog to digital converter (SAR ADC) and a method of linearity calibration therein are provided. Each composed element Ei in a part of the composed elements includes a main constructed element Ei0 and wi sub constructed element Ei1, Ei2, . . . , Eiwi. The SAR ADC selects a part of the sub constructed elements Ei1, Ei2, . . . , Eiwi and make them non-functional when a missing decision level is caused by the composed element Ei. An overlap cancellation to the obtained missing code numbers is performed, compensation coefficients are updated according to the missing code numbers after the overlap cancellation, and a compensation to the corresponding digital value is performed according to the compensation coefficients. The present disclosure prevents the necessity of matching each composed element of the DAC in the SAR ADC.
摘要翻译：提供逐次逼近寄存器模数转换器（SAR ADC）及其线性校准方法。组成元件的一部分中的每个组成元素Ei包括主构造元素Ei0和wi子构造元素Ei1，Ei2。。。 i i SAR ADC选择子构造元素Ei1，Ei2的一部分。。。，Eiwi，并且当组合元素Ei导致丢失的决策级别时，它们不起作用。执行对所获得的丢失码号的重叠取消，根据重叠消除之后的丢失码号来更新补偿系数，并根据补偿系数对相应的数字值进行补偿。本公开防止在SAR ADC中匹配DAC的每个组成元件的必要性。

5. 发明申请

US20130113638A1 METHOD AND APPARATUS FOR EVALUATING WEIGHTING OF ELEMENTS OF DAC AND SAR ADC USING THE SAME 有权
标题翻译：用于评估DAC和SAR ADC元件加权的方法和装置
公开(公告)号：US20130113638A1
公开(公告)日：2013-05-09
申请号：US13338214
申请日：2011-12-27
申请人： Hung-I Chen , Chang-Yu Chen , Xuan-Lun Huang , Jiun-Lang Huang
发明人： Hung-I Chen , Chang-Yu Chen , Xuan-Lun Huang , Jiun-Lang Huang
IPC分类号： H03M1/80 , H03M1/38
CPC分类号： H03M1/1061 , H03M1/466 , H03M1/804
摘要： A method and an apparatus for evaluating weighting of elements of a DAC and a SAR ADC using the same are provided. An equivalent weighting of each composed element is obtained by adding a reference element with a reference weighting, an auxiliary DAC, and a search circuit into the SAR ADC, and the equivalent weighting is represented by the reference weighting. The SAR ADC can calculate and then obtain a correct digital output by using the calibrated equivalent weighting and the successive approximation result of each input signal. The present disclosure prevents the necessity of matching each composed element of the DAC in the SAR ADC.
摘要翻译：提供了一种用于评估DAC的元件的加权和使用其的SAR ADC的方法和装置。通过将具有参考加权的参考元素，辅助DAC和搜索电路添加到SAR ADC中，获得每个组成元件的等效加权，并且等效加权由参考加权表示。 SAR ADC可以通过使用校准的等效加权和每个输入信号的逐次逼近结果来计算并获得正确的数字输出。本公开防止在SAR ADC中匹配DAC的每个组成元件的必要性。

6. 发明授权

US08502723B2 Method and apparatus for evaluating weighting of elements of DAC and SAR ADC using the same 有权
标题翻译：用于评估DAC和SAR ADC元件的加权的方法和装置
公开(公告)号：US08502723B2
公开(公告)日：2013-08-06
申请号：US13338214
申请日：2011-12-27
申请人： Hung-I Chen , Chang-Yu Chen , Xuan-Lun Huang , Jiun-Lang Huang
发明人： Hung-I Chen , Chang-Yu Chen , Xuan-Lun Huang , Jiun-Lang Huang
IPC分类号： H03M1/34
CPC分类号： H03M1/1061 , H03M1/466 , H03M1/804
摘要： A method and an apparatus for evaluating weighting of elements of a DAC and a SAR ADC using the same are provided. An equivalent weighting of each composed element is obtained by adding a reference element with a reference weighting, an auxiliary DAC, and a search circuit into the SAR ADC, and the equivalent weighting is represented by the reference weighting. The SAR ADC can calculate and then obtain a correct digital output by using the calibrated equivalent weighting and the successive approximation result of each input signal. The present disclosure prevents the necessity of matching each composed element of the DAC in the SAR ADC.
摘要翻译：提供了一种用于评估DAC的元件的加权和使用其的SAR ADC的方法和装置。通过将具有参考加权的参考元素，辅助DAC和搜索电路添加到SAR ADC中，获得每个组成元件的等效加权，并且等效加权由参考加权表示。 SAR ADC可以通过使用校准的等效加权和每个输入信号的逐次逼近结果来计算并获得正确的数字输出。本公开防止在SAR ADC中匹配DAC的每个组成元件的必要性。

7. 发明申请

US20110209024A1 GENERATION DEVICE, CLASSIFICATION METHOD, GENERATION METHOD, AND PROGRAM 审中-公开
标题翻译：生成装置，分类方法，生成方法和程序
公开(公告)号：US20110209024A1
公开(公告)日：2011-08-25
申请号：US13124783
申请日：2009-10-05
申请人： Meng-Fan Wu , Jiun-Lang Huang , Xiaoqing Wen , Kohei Miyase
发明人： Meng-Fan Wu , Jiun-Lang Huang , Xiaoqing Wen , Kohei Miyase
IPC分类号： G06F11/00 , G01R31/3183
CPC分类号： G01R31/318547
摘要： Provided are a generation device and the like for generating a new vector whose volume can be reduced rapidly when an output pattern derived from a decompressor of a logic circuit under test includes an unspecified bit in relation to the logic circuit under test.The output pattern includes unspecified bits. In step SS1, classification unit classifies the unspecified bits and determines if an unspecified bit is an implied bit or not. The implied bit is an unspecified bit if its value is a logic value determined as logic value 0 or 1 relating to logic bits in the initial vector and according to a predetermined condition (such as compressibility) among bits in the initial vector derived from the upstream logic circuit 1. In step SS1, the unspecified bits which are not implied bits are classified as free bits. The classification unit classifies free bit sets in step SS2, and further classifies free bits to identify compatible free bit sets. The compatible free bits of output pattern can be assigned with logic values independently of each other under the predetermined condition (such as compressibility) in relation to input pattern in step SS3.
摘要翻译：提供一种用于生成新矢量的生成装置等，当从被测逻辑电路的解压缩器导出的输出模式包括关于被测逻辑电路的未指定位时，其体积可以迅速减小。输出模式包括未指定的位。在步骤SS1中，分类单元对未指定的比特进行分类，并确定未指定的比特是否是隐含比特。如果其值是确定为与初始向量中的逻辑比特相关的逻辑值0或1的逻辑值，并且根据从上游导出的初始向量中的比特之间的预定条件（诸如可压缩性），则隐含比特是未指定比特逻辑电路1.在步骤SS1中，未指定位的未指定位被分类为空闲位。分类单元将步骤SS2中的空闲位集合进行分类，并进一步对空闲位进行分类以识别兼容的空闲位集合。可以在步骤SS3中相对于输入模式的预定条件（诸如可压缩性）之间彼此独立地分配输出模式的兼容的空闲位。

8. 发明申请

US20090040199A1 APPARATUS FOR TESTING DRIVING CIRCUIT FOR DISPLAY 有权
标题翻译：用于测试显示驱动电路的装置
公开(公告)号：US20090040199A1
公开(公告)日：2009-02-12
申请号：US11942444
申请日：2007-11-19
申请人： Chuan-Che Lee , Jiun-Lang Huang , Jui-Jer Huang
发明人： Chuan-Che Lee , Jiun-Lang Huang , Jui-Jer Huang
IPC分类号： G09G5/00
CPC分类号： H03M1/56 , G09G3/006 , G09G2310/027 , H03M1/109 , Y10S345/904
摘要： An apparatus for testing a driving circuit for a display is disclosed. The apparatus includes a selecting circuit, a reference voltage generator and an analog-to-digital converter (ADC). The selecting circuit includes many input terminals and an output terminal. The input terminals are respectively coupled to many output pins of the driving circuit, while the selecting circuit is used for selecting one of the output pins to electrically connect the output terminal of the selecting circuit. The reference voltage generator is coupled to at least one of the output pins for generating a reference voltage. The ADC is coupled to the output terminal of the selecting circuit for outputting a digital value based on a difference between an output voltage outputted from the output terminal of the selecting circuit and the reference voltage produced by the reference voltage generator.
摘要翻译：公开了一种用于测试显示器的驱动电路的装置。该装置包括选择电路，参考电压发生器和模数转换器（ADC）。选择电路包括许多输入端子和输出端子。输入端子分别耦合到驱动电路的许多输出引脚，而选择电路用于选择输出引脚之一以电连接选择电路的输出端。参考电压发生器耦合到至少一个输出引脚以产生参考电压。 ADC耦合到选择电路的输出端，用于基于从选择电路的输出端输出的输出电压与由参考电压发生器产生的参考电压之差来输出数字值。

9. 发明授权

US07616147B2 Analog-to-digital converter 有权
标题翻译：模数转换器
公开(公告)号：US07616147B2
公开(公告)日：2009-11-10
申请号：US12145759
申请日：2008-06-25
申请人： Jiun-Lang Huang , Jui-Jer Huang , Chuan-Che Lee
发明人： Jiun-Lang Huang , Jui-Jer Huang , Chuan-Che Lee
IPC分类号： H03M1/12
CPC分类号： H03M1/56 , G09G3/006 , G09G2310/027 , H03M1/109 , Y10S345/904
摘要： An analog-to-digital converter (ADC) is presented. The ADC includes an error amplifier, a ramp generator, and a counting circuit. The error amplifier is used for receiving an output voltage and a reference voltage, and amplifying a difference between the output voltage and the reference voltage, so as to obtain a first voltage and a second voltage. The ramp generator is used for generating a ramp voltage which is increased along with time. The counting circuit is used for starting counting a digital value when the ramp voltage is larger than or equal to the first voltage, and stopping counting and outputting the digital value when the ramp voltage is larger than or equal to the second voltage.
摘要翻译：提出了一种模数转换器（ADC）。 ADC包括误差放大器，斜坡发生器和计数电路。误差放大器用于接收输出电压和参考电压，并且放大输出电压和参考电压之间的差，以获得第一电压和第二电压。斜坡发生器用于产生随时间增加的斜坡电压。当斜坡电压大于或等于第一电压时，计数电路用于开始计数数字值，并且当斜坡电压大于或等于第二电压时停止计数并输出数字值。

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