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1. 发明授权

US08136068B2 Methods, systems, and computer program products for implementing compact manufacturing models in electronic design automation 有权
标题翻译：用于实现电子设计自动化中的紧凑型制造模型的方法，系统和计算机程序产品
公开(公告)号：US08136068B2
公开(公告)日：2012-03-13
申请号：US12242442
申请日：2008-09-30
申请人： Li J. Song , Srini Doddi , Emmanuel Drego , Nickhil Jakatdar
发明人： Li J. Song , Srini Doddi , Emmanuel Drego , Nickhil Jakatdar
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036 , G06F17/5068
摘要： Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method or the system receives or identifies physics based data. In some embodiments, the method or the system receives or identifies the physics based data for the corresponding manufacturing process by using the golden manufacturing process model. In some embodiments, the method or the system uses the physics based data to fine tune, modify, or adjust the golden manufacturing process model. In some embodiments, the method or the system invokes the just-right module. In some embodiments, the method or the system implements the compact manufacturing model and the correct-by-design module and provides guidelines for the various stages of the electronic circuit design.
摘要翻译：公开了一种用于在电子电路设计的各个阶段期间实现紧凑的制造模型的方法，系统和计算机程序产品。在一些实施例中，该方法或系统接收或识别基于物理的数据。在一些实施例中，该方法或系统通过使用金制造过程模型来接收或识别相应制造过程的基于物理的数据。在一些实施例中，该方法或系统使用基于物理的数据来微调，修改或调整黄金制造过程模型。在一些实施例中，该方法或系统调用正确的模块。在一些实施例中，该方法或系统实现紧凑的制造模型和逐个设计模块，并为电子电路设计的各个阶段提供指导。

2. 发明申请

US20100083200A1 METHODS, SYSTEM, AND COMPUTER PROGRAM PRODCUT FOR IMPLEMENTING COMPACT MANUFACTURING MODEL IN ELECTRONIC DESIGN AUTOMATION 有权
标题翻译：电子设计自动化中实现紧凑型制造模型的方法，系统和计算机程序
公开(公告)号：US20100083200A1
公开(公告)日：2010-04-01
申请号：US12242442
申请日：2008-09-30
申请人： Li J. Song , Srini Doddi , Emmanuel Drege , Nickhil Jakatdar
发明人： Li J. Song , Srini Doddi , Emmanuel Drege , Nickhil Jakatdar
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036 , G06F17/5068
摘要： Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method or the system receives or identifies physics based data. In some embodiments, the method or the system receives or identifies the physics based data for the corresponding manufacturing process by using the golden manufacturing process model. In some embodiments, the method or the system uses the physics based data to fine tune, modify, or adjust the golden manufacturing process model. In some embodiments, the method or the system invokes the just-right module. In some embodiments, the method or the system implements the compact manufacturing model and the correct-by-design module and provides guidelines for the various stages of the electronic circuit design.
摘要翻译：公开了一种用于在电子电路设计的各个阶段期间实现紧凑的制造模型的方法，系统和计算机程序产品。在一些实施例中，该方法或系统接收或识别基于物理的数据。在一些实施例中，该方法或系统通过使用金制造过程模型来接收或识别相应制造过程的基于物理的数据。在一些实施例中，该方法或系统使用基于物理的数据来微调，修改或调整黄金制造过程模型。在一些实施例中，该方法或系统调用正确的模块。在一些实施例中，该方法或系统实现紧凑的制造模型和逐个设计模块，并为电子电路设计的各个阶段提供指导。

3. 发明授权

US08219944B2 Method and system performing block-level RC extraction 有权
标题翻译：方法和系统执行块级RC提取
公开(公告)号：US08219944B2
公开(公告)日：2012-07-10
申请号：US12490063
申请日：2009-06-23
申请人： Li J. Song , Zhan-Zhong Yao , Rachid Salik , Hao Ji , Taber Smith
发明人： Li J. Song , Zhan-Zhong Yao , Rachid Salik , Hao Ji , Taber Smith
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method, system, and computer program product are disclosed for performing RC extraction from the perspective of the block level. A translation mechanism is employed to convert from a full-chip design domain to a block-level design domain. This allows model-based prediction results to be used in the early design implementation flow when parasitic RC and timing extractions are performed, where the model-based prediction results relate to predictions of manufacturing variations such as thickness and topography.
摘要翻译：公开了从块级的角度执行RC提取的方法，系统和计算机程序产品。采用翻译机制将其从全芯片设计域转换为块级设计域。这允许在执行寄生RC和定时提取时在早期设计实现流程中使用基于模型的预测结果，其中基于模型的预测结果与制造变化如厚度和地形的预测相关。

4. 发明授权

US08312406B2 Method and system performing RC extraction 有权
标题翻译：方法和系统执行RC提取
公开(公告)号：US08312406B2
公开(公告)日：2012-11-13
申请号：US12489340
申请日：2009-06-22
申请人： Li J. Song , Taber Smith , Hao Jl , Zhan-Zhong Yao
发明人： Li J. Song , Taber Smith , Hao Jl , Zhan-Zhong Yao
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method, system, and computer program product are disclosed for performing RC extraction. The present approach can consider multiple types of manufacturing processes, and allows location-based prediction data to be used in the context of net-based analysis. RC extraction can be more accurately performed based upon net-specific top and bottom adjustments to thickness prediction that are location-based. The net-based prediction data can be used for other purposes as well, such as to perform electrical hotspot analysis, to visually display physical properties of the nets, or allow queries for other data analysis purposes.
摘要翻译：公开了用于执行RC提取的方法，系统和计算机程序产品。目前的方法可以考虑多种类型的制造过程，并且允许在基于网络的分析的背景下使用基于位置的预测数据。可以基于基于位置的厚度预测的净特定的顶部和底部调整来更精确地执行RC提取。基于网络的预测数据也可以用于其他目的，例如执行电热分析，以可视地显示网络的物理属性，或允许查询其他数据分析目的。

5. 发明授权

US07089516B2 Measurement of integrated circuit interconnect process parameters 失效
标题翻译：集成电路互连工艺参数的测量
公开(公告)号：US07089516B2
公开(公告)日：2006-08-08
申请号：US10806680
申请日：2004-03-22
申请人： Narain D. Arora , Li J. Song , Aki Fujimura
发明人： Narain D. Arora , Li J. Song , Aki Fujimura
IPC分类号： G06F17/50
CPC分类号： G01R31/2853 , G01R31/2884 , G06F17/5018 , G06F2217/78 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to techniques for measuring integrated circuit interconnect process parameters. The techniques are applicable to any non-ideally shaped interconnects made from any type of conductive materials. Test structures are fabricated within an integrated circuit. Non-destructive electrical measurements are taken from the test structures to determine coupling capacitances associated with the test structures. A field solver uses the initial process parameters to determine design coupling capacitances. An optimizer then uses the measured coupling capacitances and the design coupling capacitances to determine the interconnect process parameters.
摘要翻译：本发明涉及用于测量集成电路互连工艺参数的技术。这些技术适用于由任何类型的导电材料制成的任何非理想形状的互连。测试结构在集成电路内制造。从测试结构获取非破坏性电测量，以确定与测试结构相关联的耦合电容。场求解器使用初始过程参数来确定设计耦合电容。然后，优化器使用测量的耦合电容和设计耦合电容来确定互连工艺参数。

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