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1. 发明授权

US06854099B2 Balanced accuracy for extraction 失效
标题翻译：平衡精度提取
公开(公告)号：US06854099B2
公开(公告)日：2005-02-08
申请号：US10064300
申请日：2002-07-01
申请人： Lewis W. Dewey, III , Peter A. Habitz , Thomas G. Mitchell
发明人： Lewis W. Dewey, III , Peter A. Habitz , Thomas G. Mitchell
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method and system for performing parasitic extraction, wherein the method comprises calculating the minimum output impedance for a network-connected component comprising a plurality of ports thereby producing a labeled impedance, estimating the minimum output impedance for every net, comparing the labeled impedance with the estimated impedance, and selecting the net which needs to be extracted based on a ratio of values of the labeled impedance and the estimated impedance. The step of calculating comprises labeling every port with a minimum size of port impedance, a resistance from a port to power, and a minimum capacitance of a port-net inside the network connected component. The step of estimating comprises using a geometry of segments of the net comprising a summation of area and perimeter values of all the segments of the net, or calculating a resistance over a length of a total net versus an average width of the net.
摘要翻译：一种用于执行寄生提取的方法和系统，其中所述方法包括计算包括多个端口的网络连接部件的最小输出阻抗，从而产生标记阻抗，估计每个网络的最小输出阻抗，将标记阻抗与估计阻抗，以及基于标记阻抗值和估计阻抗的比值来选择需要提取的网络。计算步骤包括以端口阻抗的最小尺寸，从端口到电源的电阻以及网络连接组件内的端口网的最小电容来标记每个端口。估计步骤包括使用网的几何形状，其包括网的所有段的面积和周界值的总和，或者计算总网长度相对于网的平均宽度的电阻。

2. 发明授权

US06574782B1 Decoupled capacitance calculator for orthogonal wiring patterns 有权
标题翻译：用于正交布线图案的去耦电容计算器
公开(公告)号：US06574782B1
公开(公告)日：2003-06-03
申请号：US09713422
申请日：2000-11-15
申请人： L. William Dewey, III , Peter A. Habitz , Thomas G. Mitchell
发明人： L. William Dewey, III , Peter A. Habitz , Thomas G. Mitchell
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A structure and method for extracting parasitic capacitance from a multi-layer wiring structure that creates, for each wiring layer in a wiring structure, a wiring density map and measures a plurality of metal segments in a wiring layer to determine an area occupied by the metal segments. The invention calculates an up area capacitance component for each of the metal segments by multiplying the area occupied by the metal segments by a wiring density from the wiring density map of an overlying wiring layer over the metal segments and by a capacitance coefficient of the overlying wiring layer. To calculate the down area capacitance component for each of the metal segments, the invention multiplies the area occupied by the metal segments by a wiring density, from the wiring density map of an underlying wiring layer under the metal segments and by a capacitance coefficient of the underlying wiring layer. The invention combines the up area capacitance component and the down area capacitance component to form a vertical coupling capacitance component for each of the metal segments.
摘要翻译：一种用于从多层布线结构中提取寄生电容的结构和方法，其对布线结构中的每个布线层产生布线密度图，并测量布线层中的多个金属片段，以确定金属占据的面积细分。本发明通过将金属片段占据的面积乘以金属片上覆盖布线层的布线密度图和布线密度乘以覆盖布线的电容系数来计算每个金属片段的面积电容分量层。为了计算每个金属段的下降面积电容分量，本发明根据金属段下面的布线层的布线密度图和金属段的电容系数将金属段所占的面积乘以布线密度底层布线层。本发明结合了上部区域电容分量和向下区域电容分量，以形成每个金属段的垂直耦合电容分量。

3. 发明授权

US09858368B2 Integrating manufacturing feedback into integrated circuit structure design 有权
公开(公告)号：US09858368B2
公开(公告)日：2018-01-02
申请号：US13182108
申请日：2011-07-13
申请人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang , Vladmimir Zolotov
发明人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang , Vladmimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/84
摘要： Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings.

4. 发明授权

US09157956B2 Adaptive power control using timing canonicals 有权
标题翻译：使用定时规范的自适应功率控制
公开(公告)号：US09157956B2
公开(公告)日：2015-10-13
申请号：US13614564
申请日：2012-09-13
申请人： Jeanne P. Bickford , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Clarence R. Ogilvie , Tad J. Wilder , Vladimir Zolotov
发明人： Jeanne P. Bickford , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Clarence R. Ogilvie , Tad J. Wilder , Vladimir Zolotov
IPC分类号： G06F17/50 , G01R31/317 , G01R31/30
CPC分类号： G01R31/31718 , G01R31/3008
摘要： A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connected to the digital circuits, and a non-transitory storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-transitory storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.
摘要翻译：由相同的电路设计制造多个数字电路。功率控制器可操作地连接到数字电路，并且非瞬时存储介质可操作地连接到功率控制器。数字电路分为不同的电压箱，每个电压箱都有漏电极限。已经对每个数字电路进行了测试，以在对应的电压仓的相应的电流泄漏极限内运行，每个数字电路已被分类到该对应的电压仓。非瞬时存储介质存储电压仓的边界作为速度分组测试数据。功率控制器控制基于每个数字电路已被分类的每个数字电路不同地施加的电源信号和速度合并测试数据。

5. 发明授权

US09058034B2 Integrated circuit product yield optimization using the results of performance path testing 有权
标题翻译：集成电路产品产量优化使用性能路径测试的结果
公开(公告)号：US09058034B2
公开(公告)日：2015-06-16
申请号：US13570285
申请日：2012-08-09
申请人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , Jinjun Xiong
发明人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , Jinjun Xiong
IPC分类号： G06F17/50 , G05B19/418
CPC分类号： G05B19/41875 , G05B2219/32182 , G05B2219/32187 , G05B2219/32208 , G05B2219/37224 , Y02P80/30 , Y02P90/22
摘要： Disclosed are embodiments of a method, system and computer program product for optimizing integrated circuit product yield by re-centering the manufacturing line and, optionally, adjusting wafer-level chip dispositioning rules based on the results of post-manufacture (e.g., wafer-level or module-level) performance path testing. In the embodiments, a correlation is made between in-line parameter measurements and performance measurements acquired during the post-manufacture performance path testing. Then, based on this correlation, the manufacturing line can be re-centered. Optionally, an additional correlation is made between performance measurements acquired during wafer-level performance testing and performance measurements acquired particularly during module-level performance path testing and, based on this additional correlation, adjustments can be made to the wafer-level chip dispositioning rules to further minimize yield loss.
摘要翻译：公开了用于通过使生产线重新对中来优化集成电路产品产量的方法，系统和计算机程序产品的实施例，并且可选地，基于后期制造的结果调整晶片级芯片布置规则（例如，晶片级或模块级）性能路径测试。在实施例中，在后续制造性能路径测试期间获得的在线参数测量和性能测量之间进行相关。然后，基于这种相关性，生产线可以重新居中。可选地，在晶片级性能测试期间获得的性能测量和特别在模块级性能路径测试期间获得的性能测量之间进行附加的相关性，并且基于该附加相关性，可以对晶片级芯片布置规则进行调整进一步降低产量损失。

6. 发明授权

US08726201B2 Method and system to predict a number of electromigration critical elements 失效
标题翻译：预测一些电迁移关键要素的方法和系统
公开(公告)号：US08726201B2
公开(公告)日：2014-05-13
申请号：US12780138
申请日：2010-05-14
申请人： Jeanne P. Bickford , Peter A. Habitz , Baozhen Li , Paul S. McLaughlin , Dileep N. Netrabile
发明人： Jeanne P. Bickford , Peter A. Habitz , Baozhen Li , Paul S. McLaughlin , Dileep N. Netrabile
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/10
摘要： A method and system to predict a number of electromigration critical elements in semiconductor products. This method includes determining critical element factors for a plurality of library elements in a circuit design library using a design tool running on a computer device and based on at least one of an increased reliability temperature and an increased expected current. The method also includes determining a number of critical elements in a product based on: (i) numbers of respective ones of the plurality of library elements comprised in the product, and (ii) the critical element factors.
摘要翻译：一种用于预测半导体产品中多个电迁移关键元件的方法和系统。该方法包括使用运行在计算机设备上的设计工具并且基于增加的可靠性温度和增加的预期电流中的至少一个来确定电路设计库中的多个库元件的关键要素因子。该方法还包括：（i）产品中包含的多个库元素中的相应数量的数量，以及（ii）关键要素因素来确定产品中的关键元素的数量。

7. 发明申请

US20130036395A1 EFFICIENT SLACK PROJECTION FOR TRUNCATED DISTRIBUTIONS 失效
标题翻译：截断分布的有效插值投影
公开(公告)号：US20130036395A1
公开(公告)日：2013-02-07
申请号：US13197320
申请日：2011-08-03
申请人： Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Jeffrey G. Hemmett , Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang , Vladmimir Zolotov
发明人： Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Jeffrey G. Hemmett , Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang , Vladmimir Zolotov
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031
摘要： Aspects of the present invention provide solutions for projecting slack in an integrated circuit. A statistical static timing analysis (SSTA) is computed to get a set of Gaussian distributions over a plurality of variation sources in the integrated circuit. Based on the Gaussian distributions, a truncated subset and a remainder subset of the Gaussian distributions are identified. Then data factors that represent a ratio between the remainder subset and the truncated subset are obtained. These data factors are applied to the SSTA to root sum square (RSS) project the slack for the integrated circuit that takes into account the absence of the truncated subset.
摘要翻译：本发明的方面提供了用于在集成电路中突出松弛的解决方案。计算统计静态时序分析（SSTA）以在集成电路中的多个变化源上获得一组高斯分布。基于高斯分布，识别高斯分布的截断子集和余数子集。然后获得表示余数子集和截断子集之间的比率的数据因子。这些数据因子被应用于SSTA到根平方（RSS）项目，考虑到缺少截断子集的集成电路的松弛。

8. 发明申请

US20130018617A1 INTEGRATING MANUFACTURING FEEDBACK INTO INTEGRATED CIRCUIT STRUCTURE DESIGN 有权
标题翻译：集成制造反馈到集成电路结构设计
公开(公告)号：US20130018617A1
公开(公告)日：2013-01-17
申请号：US13182108
申请日：2011-07-13
申请人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang , Vladmimir Zolotov
发明人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang , Vladmimir Zolotov
IPC分类号： G06F19/00
CPC分类号： G06F17/5036 , G06F2217/84
摘要： Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings.
摘要翻译：公开了将制造反馈集成到集成电路设计中的解决方案。在一个实施例中，公开了一种计算机实现的方法，包括：为第一集成电路产品定义可接受的收益率要求; 获取关于第一集成电路产品的制造数据; 对表示第一集成电路产品中的路径的数据执行回归分析，以基于可接受的产量要求和制造数据来定义多个参数设置; 确定与参数设置相关联的投影角以满足可接受的产量要求; 以及基于投影角和多个参数设置来修改第二集成电路产品的设计。

9. 发明授权

US08217671B2 Parallel array architecture for constant current electro-migration stress testing 失效
标题翻译：用于恒流电迁移应力测试的并行阵列架构
公开(公告)号：US08217671B2
公开(公告)日：2012-07-10
申请号：US12492619
申请日：2009-06-26
申请人： Kanak B. Agarwal , Peter A. Habitz , Jerry D. Hayes , Ying Liu , Deborah M. Massey , Alvin W. Strong
发明人： Kanak B. Agarwal , Peter A. Habitz , Jerry D. Hayes , Ying Liu , Deborah M. Massey , Alvin W. Strong
IPC分类号： G01R31/00
CPC分类号： G01R31/2858
摘要： A parallel array architecture for constant current electro-migration stress testing is provided. The parallel array architecture comprises a device under test (DUT) array having a plurality of DUTs coupled in parallel and a plurality of localized heating elements associated with respective ones of the DUTs in the DUT array. The architecture further comprises DUT selection logic that isolates individual DUTs within the array. Moreover, the architecture comprises current source logic that provides a reference current and controls the current through the DUTs in the DUT array such that each DUT in the DUT array has substantially a same current density, and current source enable logic for selectively enabling portions for the current source logic. Electro-migration stress testing is performed on the DUTs of the DUT array using the heating elements, the DUT selection logic, current source logic, and current source enable logic.
摘要翻译：提供了一种用于恒流电迁移应力测试的并行阵列架构。并行阵列结构包括被测器件（DUT）阵列，其具有并联耦合的多个DUT和与DUT阵列中相应的DUT相关联的多个局部加热元件。该架构还包括DUT阵列中的各个DUT隔离的DUT选择逻辑。此外，该架构包括提供参考电流并且控制通过DUT阵列中的DUT的电流的电流源逻辑，使得DUT阵列中的每个DUT具有基本上相同的电流密度，以及电流源使能逻辑，用于选择性地使能部分电流源逻辑。使用加热元件，DUT选择逻辑，电流源逻辑和电流源使能逻辑在DUT阵列的DUT上执行电迁移应力测试。

10. 发明授权

US08108816B2 Device history based delay variation adjustment during static timing analysis 有权
标题翻译：静态时序分析期间基于设备历史的延迟变化调整
公开(公告)号：US08108816B2
公开(公告)日：2012-01-31
申请号：US12484293
申请日：2009-06-15
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Kerim Kalafala , Jeffrey P. Soreff
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Kerim Kalafala , Jeffrey P. Soreff
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/504 , G06F2217/84
摘要： A system and method for the adjustment of history based delay variation during static timing analysis of an integrated circuit design. The method may include obtaining information through sources of variability of history based components of delay variability, and a relationship between the sources of variability and one or more bounded device histories. Then, inputting history bounds for at least one signal of the integrated circuit design, and computing and propagating history bounds through at least one first segment of the integrated circuit design to at least one signal of the integrated circuit design. Further, the method may include evaluating from at least one of the propagated history bounds, device history bounds for at least one second segment of the integrated circuit design, and based on the evaluated device history bounds, adjusting at least one of a value of the history based delay variability and propagation of timing.
摘要翻译：一种用于在集成电路设计的静态时序分析期间调整基于历史的延迟变化的系统和方法。该方法可以包括通过延迟变异性的基于历史的组件的变异源获得信息，以及变异源与一个或多个有界设备历史之间的关系。然后，为集成电路设计的至少一个信号输入历史界限，并且通过集成电路设计的至少一个第一段将集成电路设计的至少一个信号计算和传播历史界限。此外，该方法可以包括从至少一个传播的历史界限评估集成电路设计的至少一个第二段的设备历史界限，以及基于所评估的设备历史界限，调整至少一个基于历史的延迟变异性和时间传播。

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