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1. 发明申请

US20100097101A1 DISTRIBUTED SUPPLY CURRENT SWITCH CIRCUITS FOR ENABLING INDIVIDUAL POWER DOMAINS 有权
标题翻译：用于启用个性电源域的分布式电源开关电路
公开(公告)号：US20100097101A1
公开(公告)日：2010-04-22
申请号：US12642651
申请日：2009-12-18
申请人： Lew G. Chua-Eoan , Matthew Levi Severson , Sorin Adrian Dobre , Tsvetomir P. Petrov , Rajat Goel
发明人： Lew G. Chua-Eoan , Matthew Levi Severson , Sorin Adrian Dobre , Tsvetomir P. Petrov , Rajat Goel
IPC分类号： H03K19/0175
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： An integrated circuit includes multiple power domains. Supply current switch circuits (SCSCs) are distributed across each power domain. When a signal is present on a control node within a SCSC, the SCSC couples a local supply bus of the power domain to a global supply bus. An enable signal path extends through the SCSCs so that an enable signal can be propagated down a chain of SCSCs from control node to control node, thereby turning the SCSCs on one by one. When the domain is to be powered up, a control circuit asserts an enable signal that propagates down a first chain of SCSCs. After a programmable amount of time, the control circuit asserts a second enable signal that propagates down a second chain. By spreading the turning on of SCSCs over time, large currents that would otherwise be associated with coupling the local and global buses together are avoided.
摘要翻译：集成电路包括多个电源域。电源电流开关电路（SCSC）分布在每个电源域上。当SCSC中的控制节点上存在信号时，SCSC将电源域的本地电源总线耦合到全局电源总线。使能信号路径延伸穿过SCSC，使得使能信号可以从SCSC链从传播控制节点传播到控制节点，从而逐个转换SCSC。当域要加电时，控制电路断言使第一链SCSC向下传播的使能信号。在可编程的时间量之后，控制电路断言向下传播第二链的第二使能信号。通过随着时间推移SCSC的接通，避免了将局部和全局总线连接在一起的大电流。

2. 发明授权

US07659746B2 Distributed supply current switch circuits for enabling individual power domains 有权
标题翻译：用于启用各个电源域的分布式电源电流开关电路
公开(公告)号：US07659746B2
公开(公告)日：2010-02-09
申请号：US11228912
申请日：2005-09-16
申请人： Lew G. Chua-Eoan , Matthew Levi Severson , Sorin Adrian Dobre , Tsvetomir P. Petrov , Rajat Goel
发明人： Lew G. Chua-Eoan , Matthew Levi Severson , Sorin Adrian Dobre , Tsvetomir P. Petrov , Rajat Goel
IPC分类号： H03K19/0175 , H03K19/094
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： An integrated circuit includes multiple power domains. Supply current switch circuits (SCSCs) are distributed across each power domain. When a signal is present on a control node within a SCSC, the SCSC couples a local supply bus of the power domain to a global supply bus. An enable signal path extends through the SCSCs so that an enable signal can be propagated down a chain of SCSCs from control node to control node, thereby turning the SCSCs on one by one. When the domain is to be powered up, a control circuit asserts an enable signal that propagates down a first chain of SCSCs. After a programmable amount of time, the control circuit asserts a second enable signal that propagates down a second chain. By spreading the turning on of SCSCs over time, large currents that would otherwise be associated with coupling the local and global buses together are avoided.
摘要翻译：集成电路包括多个电源域。电源电流开关电路（SCSC）分布在每个电源域上。当SCSC中的控制节点上存在信号时，SCSC将电源域的本地电源总线耦合到全局电源总线。使能信号路径延伸穿过SCSC，使得使能信号可以从SCSC链从传播控制节点传播到控制节点，从而逐个转换SCSC。当域要加电时，控制电路断言使第一链SCSC向下传播的使能信号。在可编程的时间量之后，控制电路断言向下传播第二链的第二使能信号。通过随着时间推移SCSC的接通，避免了将局部和全局总线连接在一起的大电流。

3. 发明授权

US08063664B2 Distributed supply current switch circuits for enabling individual power domains 有权
标题翻译：用于启用各个电源域的分布式电源电流开关电路
公开(公告)号：US08063664B2
公开(公告)日：2011-11-22
申请号：US12642651
申请日：2009-12-18
申请人： Lew G Chua-Eoan , Matthew L Severson , Sorin A Dobre , Tsvetomir P Petrov , Rajat Goel
发明人： Lew G Chua-Eoan , Matthew L Severson , Sorin A Dobre , Tsvetomir P Petrov , Rajat Goel
IPC分类号： H03K19/0175 , H03K19/094
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： An integrated circuit includes multiple power domains. Supply current switch circuits (SCSCs) are distributed across each power domain. When a signal is present on a control node within a SCSC, the SCSC couples a local supply bus of the power domain to a global supply bus. An enable signal path extends through the SCSCs so that an enable signal can be propagated down a chain of SCSCs from control node to control node, thereby turning the SCSCs on one by one. When the domain is to be powered up, a control circuit asserts an enable signal that propagates down a first chain of SCSCs. After a programmable amount of time, the control circuit asserts a second enable signal that propagates down a second chain. By spreading the turning on of SCSCs over time, large currents that would otherwise be associated with coupling the local and global buses together are avoided.
摘要翻译：集成电路包括多个电源域。电源电流开关电路（SCSC）分布在每个电源域上。当SCSC中的控制节点上存在信号时，SCSC将电源域的本地电源总线耦合到全局电源总线。使能信号路径延伸穿过SCSC，使得使能信号可以从SCSC链从传播控制节点传播到控制节点，从而逐个转换SCSC。当域要加电时，控制电路断言使第一链SCSC向下传播的使能信号。在可编程的时间量之后，控制电路断言向下传播第二链的第二使能信号。通过随着时间推移SCSC的接通，避免了将局部和全局总线连接在一起的大电流。

4. 发明授权

US09280352B2 Lookahead scanning and cracking of microcode instructions in a dispatch queue 有权
标题翻译：在调度队列中扫描和破解微码指令
公开(公告)号：US09280352B2
公开(公告)日：2016-03-08
申请号：US13307969
申请日：2011-11-30
申请人： Ramesh B. Gunna , Peter J. Bannon , Rajat Goel
发明人： Ramesh B. Gunna , Peter J. Bannon , Rajat Goel
IPC分类号： G06F9/22 , G06F9/28 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3836 , G06F9/22 , G06F9/28 , G06F9/30145 , G06F9/3017 , G06F9/3814
摘要： An apparatus and method for avoiding bubbles and maintaining a maximum instruction throughput rate when cracking microcode instructions. A lookahead pointer scans the newest entries of a dispatch queue for microcode instructions. A detected microcode instruction is conveyed to a microcode engine to be cracked into a sequence of micro-ops. Then, the sequence of micro-ops is placed in a queue, and when the original microcode instruction entry in the dispatch queue is selected for dispatch, the sequence of micro-ops is dispatched to the next stage of the processor pipeline.
摘要翻译：一种用于在破解微代码指令时避免气泡并保持最大指令吞吐率的装置和方法。先行指针扫描调度队列的最新条目以获取微代码指令。检测到的微代码指令被传送到微代码引擎以被破解成微操作序列。然后，将微操作序列放置在队列中，并且当调度队列中的原始微代码指令条目被选择用于分派时，微操作序列被分派到处理器管线的下一个阶段。

5. 发明授权

US07502516B2 System and method for providing an extensible codec architecture for digital images 有权
标题翻译：为数字图像提供可扩展编解码架构的系统和方法
公开(公告)号：US07502516B2
公开(公告)日：2009-03-10
申请号：US11062301
申请日：2005-02-17
申请人： David Albert , Frank Alva Krueger , Rajat Goel , Peter A. Gurevich , Anthony John Rolls Hodsdon , Radu C. Magarint , Thomas W. Olsen , Rahul V. Patil , Cyra S. Richardson , Robert Earl Sinclair, II , Richard S. Turner, Jr. , Eric Vandenberg , Robert A. Wlodarczyk
发明人： David Albert , Frank Alva Krueger , Rajat Goel , Peter A. Gurevich , Anthony John Rolls Hodsdon , Radu C. Magarint , Thomas W. Olsen , Rahul V. Patil , Cyra S. Richardson , Robert Earl Sinclair, II , Richard S. Turner, Jr. , Eric Vandenberg , Robert A. Wlodarczyk
IPC分类号： G06K9/36 , G06K9/46
CPC分类号： H04N19/162 , H04N19/12 , H04N19/157 , H04N19/172
摘要： An improved system and method for an extensible codec architecture for digital images is provided. Executable software code may be operably coupled to a codec manager for requesting imaging operations to be performed on a digital image. The codec manager may receive the request to perform an imaging operation on the digital image and may select an imaging component, such as a codec, from one or more imaging components registered in the computer system for performing an imaging operation on the digital image. An arbitration manager may include functionality for requesting enumeration of the operations an imaging component may perform on a particular digital image. One or more pixel format converters may then convert the pixel format in the digital image to a pixel format supported by an imaging component installed on the system.
摘要翻译：提供了用于数字图像的可扩展编解码器架构的改进的系统和方法。可执行软件代码可以可操作地耦合到编解码器管理器，用于请求对数字图像执行的成像操作。编解码器管理器可以接收对数字图像执行成像操作的请求，并且可以从登记在计算机系统中的一个或多个成像组件选择诸如编解码器的成像组件，以对数字图像执行成像操作。仲裁管理器可以包括用于请求枚举成像组件可以在特定数字图像上执行的操作的功能。然后，一个或多个像素格式转换器可以将数字图像中的像素格式转换成由安装在系统上的成像组件支持的像素格式。

6. 发明申请

US20070050602A1 Partially decoded register renamer 有权
标题翻译：部分解码寄存器重命名
公开(公告)号：US20070050602A1
公开(公告)日：2007-03-01
申请号：US11214193
申请日：2005-08-29
申请人： Wei-Han Lien , John Yong , Shyam Sundar , Rajat Goel
发明人： Wei-Han Lien , John Yong , Shyam Sundar , Rajat Goel
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3861
摘要： In one embodiment, a renamer comprises a plurality of storage locations and compare circuitry. Each storage location is assigned to a respective renameable resource and is configured to store an identifier corresponding to a youngest instruction operation that writes the respective renameable resource. Coupled to receive an input representing one or more retiring instruction identifiers corresponding to instruction operations that are being retired, the compare circuitry is configured to detect a match between at least a first identifier in a first storage location and one of the retiring identifiers. An encoded form of the identifiers is logically divided into a plurality of fields, and the input comprises a first plurality of bit vectors. Each of the first plurality of bit vectors corresponds to a respective field and includes a bit position for each possible value of the respective field.
摘要翻译：在一个实施例中，重新映射器包括多个存储位置和比较电路。每个存储位置被分配给相应的可重命名资源，并且被配置为存储对应于写入相应可重命名资源的最小指令操作的标识符。耦合以接收表示与正在退休的指令操作相对应的一个或多个退休指令标识符的输入，所述比较电路被配置为检测第一存储位置中的至少第一标识符与退出标识符之一的匹配。标识符的编码形式在逻辑上被划分为多个字段，并且输入包括第一多个比特向量。第一多个位向量中的每一个对应于相应的场，并且包括相应场的每个可能值的比特位置。

7. 发明申请

US20130138924A1 EFFICIENT MICROCODE INSTRUCTION DISPATCH 有权
标题翻译：高效的麦克风指令分配
公开(公告)号：US20130138924A1
公开(公告)日：2013-05-30
申请号：US13307969
申请日：2011-11-30
申请人： Ramesh B. Gunna , Peter J. Bannon , Rajat Goel
发明人： Ramesh B. Gunna , Peter J. Bannon , Rajat Goel
IPC分类号： G06F9/22
CPC分类号： G06F9/3836 , G06F9/22 , G06F9/28 , G06F9/30145 , G06F9/3017 , G06F9/3814
摘要： An apparatus and method for avoiding bubbles and maintaining a maximum instruction throughput rate when cracking microcode instructions. A lookahead pointer scans the newest entries of a dispatch queue for microcode instructions. A detected microcode instruction is conveyed to a microcode engine to be cracked into a sequence of micro-ops. Then, the sequence of micro-ops is placed in a queue, and when the original microcode instruction entry in the dispatch queue is selected for dispatch, the sequence of micro-ops is dispatched to the next stage of the processor pipeline.
摘要翻译：一种用于在破解微代码指令时避免气泡并保持最大指令吞吐率的装置和方法。先行指针扫描调度队列的最新条目以获取微代码指令。检测到的微代码指令被传送到微代码引擎以被破解成微操作序列。然后，将微操作序列放置在队列中，并且当调度队列中的原始微代码指令条目被选择用于分派时，微操作序列被分派到处理器管线的下一个阶段。

8. 发明申请

US20130107655A1 Lookahead Scheme for Prioritized Reads 有权
公开(公告)号：US20130107655A1
公开(公告)日：2013-05-02
申请号：US13282873
申请日：2011-10-27
申请人： Rajat Goel , Hari S. Kannan , Khurram Z. Malik
发明人： Rajat Goel , Hari S. Kannan , Khurram Z. Malik
IPC分类号： G11C8/06 , G11C8/00
CPC分类号： G06F12/0215 , G06F5/16 , G06F13/1673 , G06F2212/301 , G11C8/06 , G11C8/16
摘要： A circular queue implementing a scheme for prioritized reads is disclosed. In one embodiment, a circular queue (or buffer) includes a number of storage locations each configured to store a data value. A multiplexer tree is coupled between the storage locations and a read port. A priority circuit is configured to generate and provide selection signals to each multiplexer of the multiplexer tree, based on a priority scheme. Based on the states of the selection signals, one of the storage locations is coupled to the read port via the multiplexers of the multiplexer tree.

9. 发明申请

US20110022824A1 Address Generation Unit with Pseudo Sum to Accelerate Load/Store Operations 有权
标题翻译：地址生成单位，具有伪和，加速加载/存储操作
公开(公告)号：US20110022824A1
公开(公告)日：2011-01-27
申请号：US12506311
申请日：2009-07-21
申请人： Rajat Goel , Chen-Ju Hsieh
发明人： Rajat Goel , Chen-Ju Hsieh
IPC分类号： G06F9/30
CPC分类号： G06F9/3017 , G06F7/506 , G06F7/60 , G06F9/355 , G06F9/3824
摘要： In an embodiment, an address generation unit (AGU) is configured to generate a pseudo sum from an index portion of two or more operands. The pseudo sum may equal the index if the carry-in of the actual sum to the least significant bit of the index is a selected value (e.g. zero). The AGU may also include circuitry coupled to receive the operands and to generate the actual carry-in to the least significant bit of the index. The AGU may transmit the pseudo sum and the carry-in to a decode block for a memory array. The decode block may decode the pseudo sum into one or more one-hot vectors. The one-hot vectors may be input to muxes, and the one-hot vectors rotated by one position may be the other input. The actual carry-in may be the selection control of the mux.
摘要翻译：在一个实施例中，地址生成单元（AGU）被配置为从两个或更多个操作数的索引部分生成伪和。如果实际和到索引的最低有效位的进位是一个选定的值（例如零），那么伪和可以等于索引。 AGU还可以包括耦合以接收操作数并且生成索引的最低有效位的实际载入的电路。 AGU可以将伪和和携带发送到用于存储器阵列的解码块。解码块可以将伪和解码成一个或多个单向量向量。单热矢量可以被输入到多路复用器，并且旋转一个位置的一个热向量可以是另一个输入。实际的进位可能是多路复用器的选择控制。

10. 发明授权

US07373486B2 Partially decoded register renamer 有权
标题翻译：部分解码寄存器重命名
公开(公告)号：US07373486B2
公开(公告)日：2008-05-13
申请号：US11214193
申请日：2005-08-29
申请人： Wei-Han Lien , John K Yong , Shyam Sundar , Rajat Goel
发明人： Wei-Han Lien , John K Yong , Shyam Sundar , Rajat Goel
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3861
摘要： In one embodiment, a renamer comprises a plurality of storage locations and compare circuitry. Each storage location is assigned to a respective renameable resource and is configured to store an identifier corresponding to a youngest instruction operation that writes the respective renameable resource. Coupled to receive an input representing one or more retiring instruction identifiers corresponding to instruction operations that are being retired, the compare circuitry is configured to detect a match between at least a first identifier in a first storage location and one of the retiring identifiers. An encoded form of the identifiers is logically divided into a plurality of fields, and the input comprises a first plurality of bit vectors. Each of the first plurality of bit vectors corresponds to a respective field and includes a bit position for each possible value of the respective field.
摘要翻译：在一个实施例中，重新映射器包括多个存储位置和比较电路。每个存储位置被分配给相应的可重命名资源，并且被配置为存储对应于写入相应可重命名资源的最小指令操作的标识符。耦合以接收表示与正在退休的指令操作相对应的一个或多个退休指令标识符的输入，所述比较电路被配置为检测第一存储位置中的至少第一标识符与退出标识符之一的匹配。标识符的编码形式在逻辑上被划分为多个字段，并且输入包括第一多个比特向量。第一多个位向量中的每一个对应于相应的场，并且包括相应场的每个可能值的比特位置。

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