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    • 2. 发明授权
    • Double carrier deflection high sensitivity magnetic sensor
    • 双载波偏转高灵敏度磁传感器
    • US4939563A
    • 1990-07-03
    • US395836
    • 1989-08-18
    • Frank F. FangDenny D. Tang
    • Frank F. FangDenny D. Tang
    • G11B5/127G01R33/02G01R33/06H01L27/22H01L29/82H01L43/00H01L43/06H01L43/08
    • H01L29/82H01L43/065
    • Apparatus for a bipolar active semiconductor magnetic field sensor that has a higher sensitivity than semiconductor field sensors presently existing in the art. Specifically, the inventive sensor utilizes a semiconductor structure containing a single emitter layer, a single base layer that is overlaid over the emitter layer and two separate oppositely situated collectors located above the base layer. A bias lateral majority carrier flow is established, in preferably and respectively both the base and emitter layers (electrons in the emitter, holes in the base), that flows in opposite directions in these layers and is oriented normal (transverse) both to the direction of transistor current and to the direction of a magnetic field that is to be detected. When the magnetic field is applied to the sensor, this field imparts a Lorentz force to these carriers which causes these majority carriers to deflect in the same direction in both the emitter and base layers, respectively. The resulting deflection of these carriers, in turn, produces local Hall effect voltages, that are proportional to the strength of the magnetic field, across the emitter-base junction that locally increases the forward bias of this junction near one collector and locally decreases the forward bias of this junction near the other collector so as to exponentially increase the collector current flowing through one collector while exponentially decreasing the collector current flow through the other collector. Inasmuch as the exponential collector current flow is a very sensitive function of emitter-base voltage, the inventive sensor is substantially more sensitive than semiconductor sensors known in the art.
    • 3. 发明授权
    • Nondestructive read-out dynamic memory cell
    • US4302764A
    • 1981-11-24
    • US53471
    • 1979-06-29
    • Frank F. FangHwa N. Yu
    • Frank F. FangHwa N. Yu
    • G11C11/35G11C16/04H01L29/78
    • G11C11/35G11C16/0466
    • A MOSFET which is capable of being placed in two states, one of which is quasi-stable and a memory cell which includes such a device is disclosed. The device basically consists of a pair of diffusions of one conductivity type disposed in a substrate of opposite conductivity type. The channel region between the diffusions is ion implanted or diffused with a dopant which forms a channel of the same conductivity type as the diffusions. A gate electrode is spaced from the channel region by a thin oxide and the gate and substrate are biased so that two states of the device are possible. One is a stable, equilibrium or conducting state wherein an opposite conductivity type inversion layer is formed at the surface of the now buried channel. Another state is a quasi-stable, nonequilibrium, nonconductive state wherein the channel region between the diffusions is depleted of mobile charge carriers. This latter state, after a relatively long period of time in the order of several minutes to hours, decays to the stable or conducting state. By applying appropriately poled pulses to the gate or source of the device, the device may be switched from one of the two conducting states to the other. A dynamic memory cell which includes an addressing FET utilizes the device described above. A word line is connected to the gate of an addressing FET which utilizes as its drain the source of the storage device described above while a bit line is connected to the source of the addressing FET. The latter, when rendered conductive by a potential on its gate, applies appropriate write pulses from a pulsed source to place the storage device in one of its two possible states. One embodiment utilizes an annular or enclosed channel device while a memory cell embodiment utilizes an open channel device, the surface of the channel of which is isolated from the substrate by a surrounding recessed oxide (ROX). The channel surface isolation of the storage device is a requirement without which leakage from substrate to the surface would not permit the achievement of the two states of the device. The quasi-stable state remains for a time which is sufficient for most memory purposes and, to the extent that longer times are required, refreshing of the states is available.
    • 4. 发明授权
    • 2D/1D junction device as a Coulomb blockade gate
    • 2D / 1D连接器作为库仑封锁门
    • US5401980A
    • 1995-03-28
    • US122814
    • 1993-09-16
    • Frank F. FangRichard A. Webb
    • Frank F. FangRichard A. Webb
    • H01L29/76H01L27/12
    • B82Y30/00B82Y10/00H01L29/7606Y10S977/937
    • A junction is formed by the establishment of first and second adjacent conductivity regions having a transition therebetween from wide (2D) to narrow (1D) with respect to the electron wavelength at the Fermi level. The electrons in the wide region can be propagated at any of a continuum of energies in two dimensions while, in the narrow region, allowable energies become quantized, forming a potential barrier similar to a junction in a tunnel diode. The junction formed in this manner exhibits a Coulomb blockade effect and can be made to operate alternatively as an extremely small capacitance and a conductance to sequentially transfer single electrons, thus forming a Coulomb blockade gate. The Coulomb blockade gate can be used in an oscillator or in digital counting and memory applications.
    • 通过建立相对于费米能级的电子波长的从宽(2D)到窄(1D)之间的过渡的第一和第二相邻导电区域的建立形成结。 宽区域中的电子可以在二维能量中的任何一个能量传播,而在窄区域中允许的能量被量化,形成类似于隧道二极管中的结的势垒。 以这种方式形成的接头表现出库仑阻塞效应,并且可以作为极小的电容和电导顺序地操作以依次传送单个电子,从而形成库仑封锁门。 库仑封锁门可用于振荡器或数字计数和存储器应用。
    • 6. 发明授权
    • Amorphous thin film transistor device
    • 非晶薄膜晶体管器件
    • US4757361A
    • 1988-07-12
    • US889137
    • 1986-07-23
    • Marc H. BrodskyFrank F. Fang
    • Marc H. BrodskyFrank F. Fang
    • H01L27/12H01L23/482H01L29/78H01L29/786H01L29/04
    • H01L29/78642H01L23/4825H01L2924/0002
    • A thin film transistor technology where a gate member on a substrate surface is in electric field influenceable proximity to active semiconductor devices in the direction normal to the substrate surface and the ohmic electrodes of the active device are parallel with the substrate surface. The gate is formed on the substrate and conformal coatings of insulator and semiconductor are provided over it. A metal is deposited from the direction normal to the surface that is thicker in the horizontal dimension than the vertical so as to be susceptible to an erosion operation such as a dip etch which separates the metal into self-aligned contact areas on each side of a semiconductor device channel without additional masking. Self-alignment of the source, drain and gate can be achieved by insulator additions above and under the gate fabricated without additional masking.
    • 一种薄膜晶体管技术,其中衬底表面上的栅极部件在垂直于衬底表面的方向上有源半导体器件的有源电极中的电场和有源器件的欧姆电极的电场平行于衬底表面。 栅极形成在基板上,并在其上提供绝缘体和半导体的保形涂层。 金属从垂直于表面的方向沉积在水平尺寸上比垂直方向更厚,以便易于受到诸如浸渍蚀刻的侵蚀操作的影响,该浸渍蚀刻将金属分成金属的每一侧上的自对准接触区域 半导体器件通道无需额外掩蔽。 源极,漏极和栅极的自对准可以通过在没有附加掩模的情况下制造的栅极上方和下方的绝缘体添加来实现。
    • 9. 发明授权
    • Semiconductor inversion layer transistor
    • 半导体反型层晶体管
    • US4326208A
    • 1982-04-20
    • US134235
    • 1980-03-26
    • Frank F. FangGeorge A. Sai-Halasz
    • Frank F. FangGeorge A. Sai-Halasz
    • H01L21/331H01L29/205H01L29/73H01L29/737H01L29/80H01L29/161
    • H01L29/205H01L29/7373
    • A semiconductor inversion layer transistor which is compatible with semiconductor fabrication technology, and an integrated circuit which incorporates a plurality of such transistors. In one embodiment of the transistor, a P type indium arsenide base and a P type gallium antimonide emitter are used while the collector can be made of either P type gallium antimonide or N type indium arsenide. By the nature of the band alignment at the interface, the indium arsenide base has its Fermi level pinned in the conduction ban at the base-emitter junction and an assymetrically conducting charge barrier which is formed at this junction is preferential to injection of carriers flowing from the emitter to the base rather than vice versa. When the base-emitter junction is forward biased the electrons at the junction are projected across the base with minimal hole injection from base to emitter, thus providing a high gain transistor having excellent high frequency characteristics.
    • 与半导体制造技术兼容的半导体反型层晶体管,以及并入有多个这样的晶体管的集成电路。 在晶体管的一个实施例中,使用P型砷化铟碱基和P型锑化镓发射极,而集电极可由P型锑化镓或N型砷化铟制成。 通过界面处的带对准性质,砷化铟锡基底在其基极 - 发射极结处的导通禁止中具有费米能级,并且在该结处形成的非对称传导电荷势垒优先于从 发射器到基极,反之亦然。 当基极 - 发射极结正向偏置时,结点处的电子通过基极到发射极的最小空穴注入而投射到基极上,从而提供具有优异高频特性的高增益晶体管。