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    • 2. 发明授权
    • Programmable pre-emphasis circuit for serial ATA
    • 串行ATA可编程预加重电路
    • US07319705B1
    • 2008-01-15
    • US10277449
    • 2002-10-22
    • Lei WuTimothy Hu
    • Lei WuTimothy Hu
    • H04J3/04
    • G06F13/4072H04L25/0292H04L25/03025
    • A high-speed serial ATA physical layer transmits data over a communications medium using a serial ATA protocol. A serial ATA control circuit controls operation of the serial ATA physical layer. A serial ATA multiplexer outputs a serial ATA signal and has a plurality of input lines for receiving input data and a control input that communicates with the serial ATA control circuit. A serial ATA analog front end includes a first differential driver that communicates with the serial ATA multiplexer and provides a first gain to the serial ATA signal and a serial ATA pre-emphasis circuit that provides pre-emphasis to the serial ATA signal to alter a transmission characteristic of the serial ATA signal.
    • 高速串行ATA物理层使用串行ATA协议在通信介质上传输数据。 串行ATA控制电路控制串行ATA物理层的操作。 串行ATA多路复用器输出串行ATA信号,并具有用于接收输入数据的多条输入线和与串行ATA控制电路通信的控制输入。 串行ATA模拟前端包括与串行ATA多路复用器通信并向串行ATA信号提供第一增益的第一差分驱动器和为串行ATA信号提供预加重以改变传输的串行ATA预加重电路 串行ATA信号的特点。
    • 3. 发明授权
    • Programmable pre-emphasis circuit for serial ATA
    • 串行ATA可编程预加重电路
    • US08311064B1
    • 2012-11-13
    • US12792247
    • 2010-06-02
    • Lei WuTimothy Hu
    • Lei WuTimothy Hu
    • G06F13/40H04J3/04
    • G06F13/4072H04L25/0292H04L25/03025
    • A transmitter including an analog front end configured to receive a serial signal; a control circuit configured to generate a first gain signal and a second gain signal based on a characteristic of a serial channel; a first amplifier is configured to amplify the serial signal to generate a first amplified signal based on the first gain signal; a first delay device configured to delay the serial signal to generate a first delayed signal; a second amplifier configured to amplify the first delayed signal to generate a second amplified signal based on the second gain signal; and at least one summer is configured to sum the first amplified signal and the second amplified signal to generate an output signal. The output signal is transmitted on the serial channel.
    • 一种发射机,包括被配置为接收串行信号的模拟前端; 控制电路,被配置为基于串行通道的特性产生第一增益信号和第二增益信号; 第一放大器被配置为基于第一增益信号放大串行信号以产生第一放大信号; 第一延迟装置,被配置为延迟所述串行信号以产生第一延迟信号; 第二放大器,被配置为基于所述第二增益信号放大所述第一延迟信号以产生第二放大信号; 并且至少一个加法器被配置为对第一放大信号和第二放大信号求和以产生输出信号。 输出信号在串行通道上传输。
    • 5. 发明授权
    • Visual language modeling for image classification
    • 图像分类的视觉语言建模
    • US08126274B2
    • 2012-02-28
    • US11847959
    • 2007-08-30
    • Mingjing LiWei-Ying MaZhiwei LiLei Wu
    • Mingjing LiWei-Ying MaZhiwei LiLei Wu
    • G06K9/62
    • G06K9/4685G06K9/4642G06K9/6278
    • Systems and methods for visual language modeling for image classification are described. In one aspect the systems and methods model training images corresponding to multiple image categories as matrices of visual words. Visual language models are generated from the matrices. In view of a given image, for example, provided by a user or from the Web, the systems and methods determine an image category corresponding to the given image. This image categorization is accomplished by maximizing the posterior probability of visual words associated with the given image over the visual language models. The image category, or a result corresponding to the image category, is presented to the user.
    • 描述了用于图像分类的视觉语言建模的系统和方法。 在一个方面,系统和方法将对应于多个图像类别的训练图像建模为视觉词的矩阵。 视觉语言模型是从矩阵生成的。 考虑到例如由用户或从Web提供的给定图像,系统和方法确定对应于给定图像的图像类别。 这种图像分类是通过在视觉语言模型上最大化与给定图像相关联的视觉词的后验概率来实现的。 图像类别或与图像类别对应的结果被呈现给用户。
    • 6. 发明授权
    • Architectures, circuits, systems and methods for reducing latency in data communications
    • 用于减少数据通信延迟的架构,电路,系统和方法
    • US07835425B1
    • 2010-11-16
    • US12330218
    • 2008-12-08
    • Pantas SutardjaLei WuHongying Sheng
    • Pantas SutardjaLei WuHongying Sheng
    • H03K11/00H04L25/60H04L25/64
    • G06F13/405
    • Circuits, architectures, systems and methods for facilitating data communications and/or reducing latency in data communications. The architecture includes a clock recovery loop receiving data from a host device and providing a recovered clock signal, a filter circuit receiving recovered clock signal information and providing a control signal that adjusts the transmitter clock in response to recovered clock signal information and the two clock signals, and a transmitter receiving the control signal and transmitting data to a destination device in accordance with the transmitter clock. The circuitry generally includes a clock alignment block receiving first and second periodic signals and providing a control signal in response thereto, a filter for first periodic signal information, and a logic circuit configured to combine the control signal and the filtered information, thereby providing an adjustment signal for the second periodic signal. The systems generally relate to those that include the present architecture and/or circuit. The method generally includes determining a phase difference between first and second periodic signals, one of the periodic signals being recovered from a data stream; adjusting the other periodic signal in response to the phase difference and filtered information from the recovered periodic signal; and transmitting the data stream in accordance with said adjusted periodic signal. The present invention advantageously eliminates a FIFO memory in the data path, thereby reducing transceiver latency and improving system performance.
    • 用于促进数据通信和/或减少数据通信中的延迟的电路,架构,系统和方法。 该架构包括时钟恢复环路,其接收来自主机设备的数据并提供恢复的时钟信号,滤波器电路接收恢复的时钟信号信息,并提供响应于恢复的时钟信号信息和两个时钟信号调整发射机时钟的控制信号 以及接收控制信号并根据发射机时钟向目的地设备发送数据的发射机。 电路通常包括时钟对准块,其接收第一和第二周期信号并响应于此提供控制信号,用于第一周期性信号信息的滤波器以及被配置为组合控制信号和滤波信息的逻辑电路,由此提供调整 信号用于第二周期信号。 系统通常涉及包括本架构和/或电路的系统。 该方法通常包括确定第一和第二周期信号之间的相位差,从数据流中恢复一个周期信号; 响应于来自恢复的周期信号的相位差和滤波信息调整另一周期信号; 以及根据所述调整的周期信号发送数据流。 本发明有利地消除数据路径中的FIFO存储器,从而减少收发机等待时间并提高系统性能。