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    • 2. 发明授权
    • Signal processing system having an ADC delta-sigma modulator with single-ended input and feedback signal inputs
    • 信号处理系统具有具有单端输入和反馈信号输入的ADCΔ-Σ调制器
    • US06972705B1
    • 2005-12-06
    • US11011732
    • 2004-12-14
    • Xiaofan FeiJohann GaboriauJohn L. Melanson
    • Xiaofan FeiJohann GaboriauJohn L. Melanson
    • H03M3/00H03M3/04
    • H03M3/39H03M3/424H03M3/452
    • Signal processing systems described herein include an analog-to-digital delta sigma modulator to process a single-ended input signal using a single-ended analog feedback reference signal. The delta sigma modulator includes a switched capacitor circuit that integrates a difference between the single-ended input signal and the single-ended analog feedback signal derived from a quantization output of the delta sigma modulator. Embodiments of the switched capacitor circuit allow the delta sigma modulator to be implemented with fewer switches, less complicated reference signal generators, and smaller capacitors relative to conventional counterparts. Thus, embodiments of the delta sigma modulator described herein can cost less to build and use less power. Embodiments of the signal processing systems can be implemented in single and multi-bit delta sigma modulators and various sampling topologies, including single and double sampling topologies.
    • 本文描述的信号处理系统包括使用单端模拟反馈参考信号来处理单端输入信号的模数转换ΔΣ调制器。 ΔΣ调制器包括开关电容器电路,其对单端输入信号和从Δ-Σ调制器的量化输出得到的单端模拟反馈信号之间的差进行积分。 开关电容器电路的实施例允许使用更少的开关,较不复杂的参考信号发生器和相对于常规对应物的较小电容器来实现Δ-Σ调制器。 因此,本文描述的Δ-Σ调制器的实施例可以降低构建和使用较少功率的成本。 信号处理系统的实施例可以在单位和多位ΔΣ调制器和各种采样拓扑中实现,包括单采样和双采样拓扑。
    • 8. 发明授权
    • Hysteretic buck converter having dynamic thresholds
    • 迟滞降压转换器具有动态阈值
    • US08008902B2
    • 2011-08-30
    • US12145807
    • 2008-06-25
    • John L. MelansonLei Ding
    • John L. MelansonLei Ding
    • G05F1/42
    • H02M3/1563H02M2001/0019H02M2001/0032Y02B70/16
    • A hysteretic buck converter provides improved regulation control, in particular for buck converter standby operation. A comparison circuit compares the output voltage of the buck converter to a waveform that is generated from an indication of the output current of the converter, so that the turn-on time of the converter is advanced as the output current demand increases. The resulting action anticipates a reduction in output voltage due to the increased current, preventing an excursion of the output voltage below the ripple voltage minimum. The turn-off time of the converter is controlled by an upper threshold that limits the ripple voltage maximum. The output current indication may be a measurement of output current, or may be a dynamic value calculated from the input voltage and the output voltage waveform.
    • 迟滞降压转换器提供改进的调节控制,特别是对于降压转换器待机操作。 比较电路将降压转换器的输出电压与从转换器的输出电流的指示产生的波形进行比较,使得转换器的导通时间随着输出电流需求的增加而提前。 所产生的动作预期由于增加的电流而导致的输出电压降低,防止输出电压偏离低于纹波电压的最小值。 转换器的关断时间由限制纹波电压最大值的上限阈值控制。 输出电流指示可以是输出电流的测量值,或者可以是从输入电压和输出电压波形计算出的动态值。
    • 9. 发明授权
    • Non-integer decimation using cascaded intergrator-comb filter
    • 使用级联集成梳状滤波器的非整数抽取
    • US07196648B1
    • 2007-03-27
    • US11317546
    • 2005-12-23
    • Lei DingJohn L. MelansonXaiofan FeiJohann Gaboriau
    • Lei DingJohn L. MelansonXaiofan FeiJohann Gaboriau
    • H03M1/66
    • H03H17/0685H03H17/0671
    • A non-integer decimation filter for decimating an input value includes a first integrator for integrating the input value in an input sample domain at an input sample rate and for generating a first integral of the input value at its output and a second integrator for integrating the first integral of the input value in the input sample domain at the input sample rate and for generating a second integral at its output. A calculation network is coupled to the outputs of the first and second integrators for combining the outputs of the first and second integrators with corresponding coefficients to generate intermediate output values in an output sample domain. A differentiator is configured to receive the intermediate output values from the calculation network and to generate a decimated output value at an output sample rate in which the output sample rate has a non-integer factor with respect to the input sample rate.
    • 用于对输入值进行抽取的非整数抽取滤波器包括:第一积分器,用于以输入采样率对输入采样域中的输入值进行积分,并在其输出端产生输入值的第一积分;以及第二积分器, 在输入采样率的输入采样域中的输入值的第一个积分,并在其输出端产生第二个积分。 计算网络耦合到第一和第二积分器的输出,用于将第一和第二积分器的输出与相应系数组合,以在输出样本域中产生中间输出值。 微分器被配置为从计算网络接收中间输出值,并且以输出采样率产生相对于输入采样率的非整数因子的输出采样率的抽取输出值。
    • 10. 发明申请
    • HYSTERETIC BUCK CONVERTER HAVING DYNAMIC THRESHOLDS
    • 具有动态阈值的HYSTERETIC BUCK转换器
    • US20090322300A1
    • 2009-12-31
    • US12145807
    • 2008-06-25
    • John L. MelansonLei Ding
    • John L. MelansonLei Ding
    • G05F1/10
    • H02M3/1563H02M2001/0019H02M2001/0032Y02B70/16
    • A hysteretic buck converter provides improved regulation control, in particular for buck converter standby operation. A comparison circuit compares the output voltage of the buck converter to a waveform that is generated from an indication of the output current of the converter, so that the turn-on time of the converter is advanced as the output current demand increases. The resulting action anticipates a reduction in output voltage due to the increased current, preventing an excursion of the output voltage below the ripple voltage minimum. The turn-off time of the converter is controlled by an upper threshold that limits the ripple voltage maximum. The output current indication may be a measurement of output current, or may be a dynamic value calculated from the input voltage and the output voltage waveform.
    • 迟滞降压转换器提供改进的调节控制,特别是对于降压转换器待机操作。 比较电路将降压转换器的输出电压与从转换器的输出电流的指示产生的波形进行比较,使得转换器的导通时间随着输出电流需求的增加而提前。 所产生的动作预期由于增加的电流而导致的输出电压降低,防止输出电压偏离低于纹波电压的最小值。 转换器的关断时间由限制纹波电压最大值的上限阈值控制。 输出电流指示可以是输出电流的测量值,或者可以是从输入电压和输出电压波形计算出的动态值。