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1. 发明授权

US5956252A Method and apparatus for an integrated circuit that is reconfigurable based on testing results 失效
标题翻译：用于基于测试结果可重新配置的集成电路的方法和装置
公开(公告)号：US5956252A
公开(公告)日：1999-09-21
申请号：US853303
申请日：1997-05-09
申请人： Lee K. Lau , Robert P. Bicevskis
发明人： Lee K. Lau , Robert P. Bicevskis
IPC分类号： G01R31/3185 , G06F11/00 , G06F11/20 , G06F15/78 , G06F19/00
CPC分类号： G01R31/318505 , G06F11/20 , G06F15/7867
摘要： A method and apparatus for reconfiguring an integrated circuit based on testing results is accomplished by an integrated circuit that includes a first circuit, a second circuit, and configuration circuitry deposited on a single die. After testing of the die, the configuration circuitry configures the integrated circuit based on the results of the testing. If both circuits passed the testing, the configuration circuitry couples, where appropriate, the first and second circuits together. If, however, the first circuit failed the testing and the second circuit passed the testing, the configuration circuitry configures the integrated circuit as if only the second circuit were present on the die. If, however, the second circuit failed the testing and the first circuit passed the testing, the configuration circuitry configures the integrated circuit as if only the first circuit were present on the die.
摘要翻译：用于基于测试结果来重新配置集成电路的方法和装置由集成电路实现，该集成电路包括沉积在单一管芯上的第一电路，第二电路和配置电路。在芯片测试之后，配置电路根据测试结果配置集成电路。如果两个电路通过测试，配置电路在适当的情况下将第一和第二电路耦合在一起。然而，如果第一个电路测试失败，而第二个电路通过了测试，则配置电路配置集成电路，就好像芯片上只存在第二个电路一样。然而，如果第二个电路测试失败，而第一个电路通过了测试，则配置电路将集成电路配置为就像芯片上只存在第一个电路一样。

2. 发明授权

US06351681B1 Method and apparatus for a multi-chip module that is testable and reconfigurable based on testing results 有权
标题翻译：基于测试结果可测试和可重新配置的多芯片模块的方法和装置
公开(公告)号：US06351681B1
公开(公告)日：2002-02-26
申请号：US09197720
申请日：1998-11-23
申请人： David Chih , Lee K. Lau , Keith S. K. Lee
发明人： David Chih , Lee K. Lau , Keith S. K. Lee
IPC分类号： G06F1900
CPC分类号： G01R31/318513 , G01R31/318505 , G06F11/20 , G06F15/7867
摘要： A method and apparatus for a multi-chip module that is testable and reconfigurable based on testing results is accomplished by a multi-chip module that includes a first circuit disposed on a first chip substrate, a second circuit disposed on second chip substrate, and an interconnecting substrate operably coupled to the first chip substrate and the second chip substrate. The interconnecting substrate connects the first circuit to the second circuit. The interconnecting substrate includes external connectors for accessing signals within the multi-chip module, which allow the multi-chip module to be fully tested. This testing may include isolating the first circuit and/or the second circuit by disabling other circuits in order to allow each of the circuits to be exercised without interference from other circuits. After testing the multi-chip module, configuration circuitry included on the multi-chip module may be used to reconfigure the multi-chip module based on results of the testing.
摘要翻译：一种基于测试结果可测试和可重新配置的多芯片模块的方法和装置由多芯片模块实现，该多芯片模块包括设置在第一芯片基板上的第一电路，以及设置在第二芯片基板上的第二电路，互连衬底，其可操作地耦合到第一芯片衬底和第二芯片衬底。互连基板将第一电路连接到第二电路。互连基板包括用于访问多芯片模块内的信号的外部连接器，其允许多芯片模块被完全测试。该测试可以包括通过禁用其他电路来隔离第一电路和/或第二电路，以便允许每个电路在没有来自其他电路的干扰的情况下被行使。在测试多芯片模块之后，可以使用包括在多芯片模块上的配置电路基于测试结果来重新配置多芯片模块。

3. 发明授权

US06209075B1 Method and apparatus for extending memory of an integrated circuit 失效
标题翻译：用于扩展集成电路的存储器的方法和装置
公开(公告)号：US06209075B1
公开(公告)日：2001-03-27
申请号：US08841284
申请日：1997-04-29
申请人： Lee K. Lau
发明人： Lee K. Lau
IPC分类号： G06F1200
CPC分类号： G06F15/7867 , G01R31/318505 , G06F11/20
摘要： A method and apparatus for extending an on-chip processing device's access to memory are accomplished by depositing a processing circuit, memory, and configuration circuitry on a die. When the memory has sufficient digital storage capabilities for the processing circuit, the configuration circuitry directly couples an address bus and data bus between the memory and the processing device. When the memory does not have sufficient digital storage capabilities for the processing circuit, the configuration circuitry reconfigures the memory. In additional, the configuration circuitry extends the address bus to an external memory and combines the internal data bus with an external data bus. Configured in this manner, the processing device can access both the on-chip memory and the external memory as a single addressable memory, thereby increasing the memory available to the processing circuit.
摘要翻译：通过在芯片上沉积处理电路，存储器和配置电路来实现用于扩展片上处理器件对存储器的访问的方法和装置。当存储器具有用于处理电路的足够的数字存储能力时，配置电路在存储器和处理设备之间直接耦合地址总线和数据总线。当存储器对于处理电路没有足够的数字存储能力时，配置电路重新配置存储器。此外，配置电路将地址总线扩展到外部存储器，并将内部数据总线与外部数据总线组合。以这种方式配置，处理设备可以作为单个可寻址存储器访问片上存储器和外部存储器，从而增加处理电路可用的存储器。

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