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1. 发明授权

US06487131B1 Method and apparatus for testing a CAM addressed cache 失效
标题翻译：用于测试CAM寻址缓存的方法和装置
公开(公告)号：US06487131B1
公开(公告)日：2002-11-26
申请号：US09475491
申请日：1999-12-30
申请人： Lawrence T. Clark , Jay B. Miller
发明人： Lawrence T. Clark , Jay B. Miller
IPC分类号： G11C700
CPC分类号： G11C15/00 , G11C29/12
摘要： In one embodiment, an array of content addressable memory (CAM) cells include a first plurality of CAM cells and a second plurality of CAM cells. The second plurality of CAM cells has a width sufficient to address a height of the array. A first plurality of CAM drivers are coupled to the array to drive the first plurality of CAM cells. The first plurality of CAM drivers prevent the first plurality of CAM cells from participating in a match when the array is in a test mode.
摘要翻译：在一个实施例中，内容可寻址存储器（CAM）单元的阵列包括第一多个CAM单元和第二多个CAM单元。第二组多个CAM单元具有足以解决阵列高度的宽度。第一多个CAM驱动器耦合到阵列以驱动第一多个CAM单元。当阵列处于测试模式时，第一组多个CAM驱动程序防止第一多个CAM单元参与匹配。

2. 发明授权

US06944713B2 Low power set associative cache 有权
标题翻译：低功耗组相关缓存
公开(公告)号：US06944713B2
公开(公告)日：2005-09-13
申请号：US10174668
申请日：2002-06-18
申请人： Lawrence T. Clark , Jay B. Miller
发明人： Lawrence T. Clark , Jay B. Miller
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0864 , G06F12/0846 , G06F2212/1028 , Y02D10/13
摘要： A processor having an L1 cache memory that may use a compare circuit to determine matches of stored tag information against an address and gate sense amps of the cache memory with a cache-hit signal.
摘要翻译：一种具有L1高速缓冲存储器的处理器，其可以使用比较电路来确定存储的标签信息与高速缓存存储器的地址和门检测放大器的匹配以及高速缓存命中信号。

3. 发明授权

US06909651B2 Method and apparatus for testing a CAM addressed cache 失效
标题翻译：用于测试CAM寻址缓存的方法和装置
公开(公告)号：US06909651B2
公开(公告)日：2005-06-21
申请号：US10803408
申请日：2004-03-17
申请人： Lawrence T. Clark , Jay B. Miller
发明人： Lawrence T. Clark , Jay B. Miller
IPC分类号： G11C15/00 , G11C29/12 , G11C11/00
CPC分类号： G11C15/00 , G11C29/12
摘要： In one embodiment, an array of content addressable memory (CAM) cells include a first plurality of CAM cells and a second plurality of CAM cells. The second plurality of CAM cells has a width sufficient to address a height of the array. A first plurality of CAM drivers are coupled to the array to drive the first plurality of CAM cells. The first plurality of CAM drivers prevent the first plurality of CAM cells from participating in a match when the array is in a test mode.
摘要翻译：在一个实施例中，内容可寻址存储器（CAM）单元的阵列包括第一多个CAM单元和第二多个CAM单元。第二组多个CAM单元具有足以解决阵列高度的宽度。第一多个CAM驱动器耦合到阵列以驱动第一多个CAM单元。当阵列处于测试模式时，第一组多个CAM驱动程序防止第一多个CAM单元参与匹配。

4. 发明授权

US06744655B2 Method and apparatus for testing a CAM addressed cache 失效
标题翻译：用于测试CAM寻址缓存的方法和装置
公开(公告)号：US06744655B2
公开(公告)日：2004-06-01
申请号：US10261395
申请日：2002-09-30
申请人： Lawrence T. Clark , Jay B. Miller
发明人： Lawrence T. Clark , Jay B. Miller
IPC分类号： G11C1500
CPC分类号： G11C15/00 , G11C29/12
摘要： In one embodiment, an array of content addressable memory (CAM) cells include a first plurality of CAM cells and a second plurality of CAM cells. The second plurality of CAM cells has a width sufficient to address a height of the array. A first plurality of CAM drivers are coupled to the array to drive the first plurality of CAM cells. The first plurality of CAM drivers prevent the first plurality of CAM cells from participating in a match when the array is in a test mode.
摘要翻译：在一个实施例中，内容可寻址存储器（CAM）单元的阵列包括第一多个CAM单元和第二多个CAM单元。第二组多个CAM单元具有足以解决阵列高度的宽度。第一多个CAM驱动器耦合到阵列以驱动第一多个CAM单元。当阵列处于测试模式时，第一组多个CAM驱动程序防止第一多个CAM单元参与匹配。

5. 发明授权

US07480189B2 Cross-coupled write circuit 失效
标题翻译：交叉耦合写电路
公开(公告)号：US07480189B2
公开(公告)日：2009-01-20
申请号：US10251674
申请日：2002-09-20
申请人： Lawrence T. Clark , Jay B. Miller
发明人： Lawrence T. Clark , Jay B. Miller
IPC分类号： G11C7/10
CPC分类号： G11C7/1096 , G06F12/0893 , G11C7/1048 , G11C7/1078 , G11C7/12 , G11C2207/002
摘要： A write circuit structure may be used to transfer data between global bit lines and local bit lines of a cache. The write circuit structure located between the hierarchical bit lines may be buffers in parallel with P-channel devices in one embodiment or cross-coupled P-channel and N-channel devices in another embodiment.
摘要翻译：写电路结构可用于在高速缓存的全局位线和本地位线之间传送数据。位于分层位线之间的写入电路结构可以是在一个实施例中与P沟道器件并联的缓冲器，或者在另一实施例中可以是交叉耦合的P沟道和N沟道器件。

6. 发明申请

US20180046580A1 MULTI-MODE RADIATION HARDENED MULTI-CORE MICROPROCESSORS 审中-公开
公开(公告)号：US20180046580A1
公开(公告)日：2018-02-15
申请号：US15672810
申请日：2017-08-09
申请人： Lawrence T. Clark
发明人： Lawrence T. Clark
IPC分类号： G06F12/0897
摘要： Systems and methods for multi-mode radiation hardened multi-core microprocessors are disclosed. In some embodiments, a triplicated circuit includes a first core logic, a second core logic, a third core logic, and bus arbitration and control circuitry. The triplicated circuit is configurable to operate in both a Triple-Modular Redundant (TMR) mode of operation and a multi-threaded mode of operation. In some embodiments, there is essentially no overhead in soft mode and low overhead (power only) in hard mode. In most applications, it is expected that portions of missions require very hard systems (e.g., landing) where a failure is catastrophic. However, other portions require essentially no hardening (digital signal processor and signal processing activities) but much better throughput. Consequently, there is a huge opportunity to develop computer processors with low overhead in soft mode and unprecedented hardness in hard mode.

7. 发明申请

US20160065243A1 RADIATION HARDENING ARCHITECTURAL EXTENSIONS FOR A RADIATION HARDENED BY DESIGN MICROPROCESSOR 审中-公开
标题翻译：通过设计微处理器硬化辐射的辐射硬化结构扩展
公开(公告)号：US20160065243A1
公开(公告)日：2016-03-03
申请号：US14837361
申请日：2015-08-27
申请人： Dan Wheeler Patterson , Lawrence T. Clark
发明人： Dan Wheeler Patterson , Lawrence T. Clark
IPC分类号： H03M13/11 , G06F9/30 , H03M13/00
CPC分类号： G06F9/30145 , G06F9/3861 , G06F9/3863 , G06F11/00
摘要： This disclosure relates generally to processors and methods of operating the same. In particular, this disclosure relates to components for correcting soft errors in a processor. In one embodiment, a processor includes an instruction decoder and an exception handler. The instruction decoder is configured to receive one or more soft error correction instructions and decode the one or more soft error correction instructions. Additionally, an exception handler is configured to execute the one or more soft error correction instructions so as to correct one or more soft errors. In this manner, the processor is capable of correcting soft errors that are the result of radiation strikes.
摘要翻译：本公开一般涉及其操作处理器和方法。特别地，本公开涉及用于校正处理器中的软错误的组件。在一个实施例中，处理器包括指令解码器和异常处理程序。指令解码器被配置为接收一个或多个软错误校正指令并对一个或多个软错误校正指令进行解码。此外，异常处理程序被配置为执行一个或多个软错误校正指令，以便校正一个或多个软错误。以这种方式，处理器能够校正作为辐射打击结果的软错误。

8. 发明授权

US09038012B2 Sequential state elements in triple-mode redundant (TMR) state machines 有权
标题翻译：三模冗余（TMR）状态机中的顺序状态元素
公开(公告)号：US09038012B2
公开(公告)日：2015-05-19
申请号：US14304155
申请日：2014-06-13
申请人： Lawrence T. Clark , Nathan D. Hindman , Dan Wheeler Patterson
发明人： Lawrence T. Clark , Nathan D. Hindman , Dan Wheeler Patterson
IPC分类号： G06F17/50 , H03K19/173 , H03K19/003
CPC分类号： G06F17/5072 , G06F17/505 , H03K19/00315
摘要： The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. The SSEs has a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit.
摘要翻译：本公开一般涉及形成为诸如CMOS的半导体衬底上的集成电路的三冗余顺序状态（TRSS）机器，以及设计三重冗余顺序状态机的计算机化方法和系统。本公开中特别关注的是用于采样和保持位状态的顺序状态元素（SSE）。位状态的采样和保持由时钟信号同步，从而允许在TRSS机器中流水线化。具体地，时钟信号可以在第一时钟状态和第二时钟状态之间振荡，以根据由时钟状态提供的定时使SSE的操作同步。 SSEs具有自我纠正机制，可防止辐射诱发的软错误。 SSE可以设置在TRSS机器的管线电路中，以接收和存储由管线电路内的组合电路产生的位信号的位状态。

9. 发明授权

US08995204B2 Circuit devices and methods having adjustable transistor body bias 有权
标题翻译：具有可调节晶体管体偏置的电路器件和方法
公开(公告)号：US08995204B2
公开(公告)日：2015-03-31
申请号：US13167625
申请日：2011-06-23
申请人： Lawrence T. Clark , Bruce McWilliams , Robert Rogenmoser
发明人： Lawrence T. Clark , Bruce McWilliams , Robert Rogenmoser
IPC分类号： G11C7/00 , G11C11/412
CPC分类号： G11C11/412
摘要： Circuits, integrated circuits devices, and methods are disclosed that may include biasable transistors with screening regions positioned below a gate and separated from the gate by a semiconductor layer. Bias voltages can be applied to such screening regions to optimize multiple performance features, such as speed and current leakage. Particular embodiments can include biased sections coupled between a high power supply voltage and a low power supply voltage, each having biasable transistors. One or more generation circuits can generate multiple bias voltages. A bias control section can couple one of the different bias voltages to screening regions of biasable transistors to provide a minimum speed and lowest current leakage for such a minimum speed.
摘要翻译：公开了电路，集成电路器件和方法，其可以包括具有位于栅极下方的屏蔽区域并通过半导体层与栅极分离的可偏置晶体管。偏置电压可以应用于这样的屏蔽区域以优化多个性能特征，例如速度和电流泄漏。特定实施例可以包括耦合在高电源电压和低电源电压之间的偏置部分，每个具有可偏置晶体管。一个或多个发电电路可以产生多个偏置电压。偏置控制部分可以将不同偏置电压之一耦合到可偏置晶体管的屏蔽区域，以提供用于这种最小速度的最小速度和最小电流泄漏。

10. 发明授权

US08860197B2 Integrated circuits secure from invasion and methods of manufacturing the same 有权
标题翻译：集成电路不受侵袭和制造方法
公开(公告)号：US08860197B2
公开(公告)日：2014-10-14
申请号：US13139955
申请日：2009-12-29
申请人： Lawrence T. Clark , David R. Allee
发明人： Lawrence T. Clark , David R. Allee
IPC分类号： H01L23/02 , H01L23/06 , H01L29/06 , H01L21/56 , H01L23/31 , H01L23/00 , H01L23/13 , G06F21/79 , G06F21/87 , H01L23/498
CPC分类号： H01L23/3121 , G06F21/79 , G06F21/87 , H01L21/56 , H01L23/13 , H01L23/49833 , H01L23/57 , H01L24/17 , H01L24/45 , H01L24/48 , H01L24/49 , H01L29/0657 , H01L2224/05554 , H01L2224/13099 , H01L2224/16 , H01L2224/451 , H01L2224/48091 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01049 , H01L2924/01087 , H01L2924/014 , H01L2924/14 , H01L2924/15787 , H01L2924/181 , H01L2924/00 , H01L2224/05599 , H01L2224/0401 , H01L2924/00012
摘要： An integrated circuit device that is secure from invasion and related methods are disclosed herein. Other embodiments are also disclosed herein.
摘要翻译：本文公开了一种防止侵入和相关方法的集成电路装置。本文还公开了其它实施例。

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