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1. 发明申请

US20090037857A1 METHODS FOR DESIGN RULE CHECKING WITH ABSTRACTED VIA OBSTRUCTIONS 有权
标题翻译：用于通过障碍物进行设计规则检查的方法
公开(公告)号：US20090037857A1
公开(公告)日：2009-02-05
申请号：US11830255
申请日：2007-07-30
申请人： Laura R. Darden , William J. Livingstone
发明人： Laura R. Darden , William J. Livingstone
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Methods of treating via obstructions during design rule checking. The method comprises examining the size of the via obstruction with respect to a minimum size and a minimum spacing constraint of a design rule. Based upon the comparison, a neighboring via count for a number of via shapes neighboring the via obstruction may be initialized to equal a positive integer. Based upon the comparison, the via obstruction may be represented with a plurality of smaller via shapes during design rule checking.
摘要翻译：在设计规则检查过程中通过障碍物进行治疗的方法。该方法包括相对于设计规则的最小尺寸和最小间距约束检查通孔阻塞的尺寸。基于比较，可以将与通孔阻塞相邻的多个通孔形状的相邻通孔计数初始化为等于正整数。基于比较，在设计规则检查期间，可以用多个较小的通孔形状来表示通孔阻塞。

2. 发明授权

US07725850B2 Methods for design rule checking with abstracted via obstructions 有权
标题翻译：抽象通过障碍物进行设计规则检查的方法
公开(公告)号：US07725850B2
公开(公告)日：2010-05-25
申请号：US11830255
申请日：2007-07-30
申请人： Laura R. Darden , William J. Livingstone
发明人： Laura R. Darden , William J. Livingstone
IPC分类号： G06F17/50 , H03K17/693 , H01L23/48
CPC分类号： G06F17/5081
摘要： Methods of treating via obstructions during design rule checking. The method comprises examining the size of the via obstruction with respect to a minimum size and a minimum spacing constraint of a design rule. Based upon the comparison, a neighboring via count for a number of via shapes neighboring the via obstruction may be initialized to equal a positive integer. Based upon the comparison, the via obstruction may be represented with a plurality of smaller via shapes during design rule checking.
摘要翻译：在设计规则检查过程中通过障碍物进行治疗的方法。该方法包括相对于设计规则的最小尺寸和最小间距约束检查通孔阻塞的尺寸。基于比较，可以将与通孔阻塞相邻的多个通孔形状的相邻通孔计数初始化为等于正整数。基于比较，在设计规则检查期间，可以用多个较小的通孔形状来表示通孔阻塞。

3. 发明授权

US06779165B2 Spacing violation checker 有权
标题翻译：间距违规检查器
公开(公告)号：US06779165B2
公开(公告)日：2004-08-17
申请号：US09836164
申请日：2001-04-18
申请人： Laura R. Darden
发明人： Laura R. Darden
IPC分类号： G06F1750
CPC分类号： G06F17/5081
摘要： A spacing violation checker that forms conductor rectangles, forms minimum spacing rectangles, identifies possible errors and checks whether possible errors are true errors allows same net spacing errors to be recognized during physical design prior to the design rules check. The software supporting the invention performs orders of magnitude faster than the design rules check solution. As such, the invention dramatically decreases the turn-around time of physical design, providing a fast solution which is available prior to final layout release.
摘要翻译：形成导体矩形的间隔冲突检查器，形成最小间距矩形，识别可能的错误并检查可能的错误是否为真错误，允许在设计规则检查之前的物理设计期间识别相同的净间距误差。支持本发明的软件比设计规则检查解决方案更快地执行数量级。因此，本发明大大减少了物理设计的周转时间，提供了在最终布局发布之前可用的快速解决方案。

4. 发明授权

US06301689B1 Spacing violation checker 失效
标题翻译：间距违规检查器
公开(公告)号：US06301689B1
公开(公告)日：2001-10-09
申请号：US09162215
申请日：1998-09-28
申请人： Laura R. Darden
发明人： Laura R. Darden
IPC分类号： G06F1750
CPC分类号： G06F17/5081
摘要： A spacing violation checker that forms conductor rectangles, forms minimum spacing rectangles, identifies possible errors and checks whether possible errors are true errors allows same net spacing errors to be recognized during physical design prior to the design rules check. The software supporting the invention performs orders of magnitude faster than the design rules check solution. As such, the invention dramatically decreases the turn-around time of physical design, providing a fast solution which is available prior to final layout release.
摘要翻译：形成导体矩形的间隔冲突检查器，形成最小间距矩形，识别可能的错误并检查可能的错误是否为真错误，允许在设计规则检查之前的物理设计期间识别相同的净间距误差。支持本发明的软件比设计规则检查解决方案更快地执行数量级。因此，本发明大大减少了物理设计的周转时间，提供了在最终布局发布之前可用的快速解决方案。

5. 发明授权

US06598206B2 Method and system of modifying integrated circuit power rails 有权
公开(公告)号：US06598206B2
公开(公告)日：2003-07-22
申请号：US09853115
申请日：2001-05-10
申请人： Laura R. Darden , Scott W. Gould , Patrick M. Ryan , Steven J. Urish
发明人： Laura R. Darden , Scott W. Gould , Patrick M. Ryan , Steven J. Urish
IPC分类号： G06F1750
CPC分类号： G06F17/5077 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A method and system for modifying power rails of an integrated circuit having improved wireability. This is accomplished by initially generating a power railing design of the integrated circuit into a three-dimensional rail based model. Next, analysis of the design is performed as to placement of the power rails in relation to neighboring elements that affects a predefined wireability. Finally, modification of a segment of each power rail that affects wireability is performed so that required power supply to the neighboring elements (e.g., pins, rails etc.) remains unaffected.

6. 发明授权

US07278127B2 Overlapping shape design rule error prevention 有权
标题翻译：重叠形状设计规则错误预防
公开(公告)号：US07278127B2
公开(公告)日：2007-10-02
申请号：US10710914
申请日：2004-08-12
申请人： Laura R. Darden , Mark R. Lasher
发明人： Laura R. Darden , Mark R. Lasher
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method, system and program product are disclosed that create new shapes at detected shape overlaps and includes those new shapes during routing and net checking when the new shapes require a larger space than any of the overlapping shapes. The invention thus detects and prevents spacing errors without the expense of time consuming design rule checking (DRC), facilitating early detection and prevention of errors.
摘要翻译：公开了一种方法，系统和程序产品，其在检测到的形状重叠处创建新形状，并且当新形状需要比任何重叠形状更大的空间时，在路由和网络检查期间包括这些新形状。本发明因此检测并防止间隔错误，而不需要费时的设计规则检查（DRC），便于早期检测和防止错误。

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