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1. 发明授权

US07750648B2 Method to quickly estimate inductance for timing models 有权
标题翻译：快速估计定时模型电感的方法
公开(公告)号：US07750648B2
公开(公告)日：2010-07-06
申请号：US12059275
申请日：2008-03-31
申请人： Eric A. Foreman , Peter A. Habitz , Mark R. Lasher , William J. Livingstone , Gregory M. Schaeffer
发明人： Eric A. Foreman , Peter A. Habitz , Mark R. Lasher , William J. Livingstone , Gregory M. Schaeffer
IPC分类号： G01R27/00
CPC分类号： G01R27/2611 , G01R27/28 , G06F17/5036 , G06F2217/84
摘要： A method of estimating an inductance delay includes determining a resistance-capacitance (RC) delay with resistances and capacitances of a network and estimating an inductance delay of the network by determining a propagation delay of an electromagnetic (EM) field across wires of the network. Additionally, the method includes determining if the RC delay is below a specified threshold and adding the estimated inductance delay to the RC delay to determine a total time to propagate voltage swings through the network if the RC delay is below the specified threshold.
摘要翻译：估计电感延迟的方法包括通过确定网络的电线（EM）场的传播延迟来确定网络的电阻和电容的电阻 - 电容（RC）延迟并估计网络的电感延迟。此外，该方法包括确定RC延迟是否低于指定的阈值，并将估计的电感延迟与RC延迟相加，以确定如果RC延迟低于指定阈值，则传播通过网络的电压摆幅的总时间。

2. 发明申请

US20090243630A1 METHOD TO QUICKLY ESTIMATE INDUCTANCE FOR TIMING MODELS 有权
标题翻译：快速估计时序模型电感的方法
公开(公告)号：US20090243630A1
公开(公告)日：2009-10-01
申请号：US12059275
申请日：2008-03-31
申请人： Eric A. Foreman , Peter A. Habitz , Mark R. Lasher , William J. Livingstone , Gregory M. Schaeffer
发明人： Eric A. Foreman , Peter A. Habitz , Mark R. Lasher , William J. Livingstone , Gregory M. Schaeffer
IPC分类号： G01R27/28
CPC分类号： G01R27/2611 , G01R27/28 , G06F17/5036 , G06F2217/84
摘要： A method of estimating an inductance delay includes determining a resistance-capacitance (RC) delay with resistances and capacitances of a network and estimating an inductance delay of the network by determining a propagation delay of an electromagnetic (EM) field across wires of the network. Additionally, the method includes determining if the RC delay is below a specified threshold and adding the estimated inductance delay to the RC delay to determine a total time to propagate voltage swings through the network if the RC delay is below the specified threshold.
摘要翻译：估计电感延迟的方法包括通过确定网络的电线（EM）场的传播延迟来确定网络的电阻和电容的电阻 - 电容（RC）延迟并估计网络的电感延迟。此外，该方法包括确定RC延迟是否低于指定的阈值，并将估计的电感延迟与RC延迟相加，以确定如果RC延迟低于指定阈值，则传播通过网络的电压摆幅的总时间。

3. 发明授权

US07725850B2 Methods for design rule checking with abstracted via obstructions 有权
标题翻译：抽象通过障碍物进行设计规则检查的方法
公开(公告)号：US07725850B2
公开(公告)日：2010-05-25
申请号：US11830255
申请日：2007-07-30
申请人： Laura R. Darden , William J. Livingstone
发明人： Laura R. Darden , William J. Livingstone
IPC分类号： G06F17/50 , H03K17/693 , H01L23/48
CPC分类号： G06F17/5081
摘要： Methods of treating via obstructions during design rule checking. The method comprises examining the size of the via obstruction with respect to a minimum size and a minimum spacing constraint of a design rule. Based upon the comparison, a neighboring via count for a number of via shapes neighboring the via obstruction may be initialized to equal a positive integer. Based upon the comparison, the via obstruction may be represented with a plurality of smaller via shapes during design rule checking.
摘要翻译：在设计规则检查过程中通过障碍物进行治疗的方法。该方法包括相对于设计规则的最小尺寸和最小间距约束检查通孔阻塞的尺寸。基于比较，可以将与通孔阻塞相邻的多个通孔形状的相邻通孔计数初始化为等于正整数。基于比较，在设计规则检查期间，可以用多个较小的通孔形状来表示通孔阻塞。

4. 发明授权

US07684969B2 Forming statistical model of independently variable parameters for timing analysis 有权
标题翻译：形成时间分析独立变量参数的统计模型
公开(公告)号：US07684969B2
公开(公告)日：2010-03-23
申请号：US11219205
申请日：2005-09-02
申请人： Peter A. Habitz , Mark R. Lasher , William J. Livingstone
发明人： Peter A. Habitz , Mark R. Lasher , William J. Livingstone
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5022
摘要： Forming of a statistical model for a set of independently variable parameters for analysis of a circuit design is disclosed. In one embodiment, a method includes establishing a timing model including delay and delay changes due to process parameter variations (Pi) that impact timing; selecting an element of the circuit design that dominates circuit delay in the timing model; determining a delay sensitivity of each of a set of derived process parameters (Vj) for the element that are linear combinations of the process parameter variations (Pi); and selecting only those derived process parameters with a high sensitivity for use in the statistical model. The invention simplifies the statistical model and reduces the number of calculations require for timing analysis. A method of performing a timing analysis using the simplified statistical model is also disclosed.
摘要翻译：公开了一组用于电路设计分析的独立可变参数的统计模型的形成。在一个实施例中，一种方法包括建立包括由于影响定时的过程参数变化（Pi）引起的延迟和延迟变化的定时模型; 选择在时序模型中支配电路延迟的电路设计元素; 确定作为所述过程参数变化（Pi）的线性组合的所述元素的一组导出过程参数（Vj）中的每一个的延迟灵敏度; 并仅选择具有高灵敏度的衍生过程参数用于统计模型。本发明简化了统计模型，并减少了时序分析所需的计算次数。还公开了使用简化统计模型执行定时分析的方法。

5. 发明授权

US07464359B2 Method for re-routing an interconnection array to improve switching behavior in a single net and an associated interconnection array structure 失效
标题翻译：用于重新路由互连阵列以改善单个网络中的交换行为和相关联的互连阵列结构的方法
公开(公告)号：US07464359B2
公开(公告)日：2008-12-09
申请号：US11277541
申请日：2006-03-27
申请人： Peter A. Habitz , William J. Livingstone
发明人： Peter A. Habitz , William J. Livingstone
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5081
摘要： Disclosed are embodiments of an interconnection array for a circuit. The interconnection array comprises a victim net that is positioned parallel to and adjacent to sections of multiple crossed aggressor nets, thereby, minimizing the exposure of the circuit to delay or false switching as a result of coupling capacitance. Also, disclosed are embodiments of an associated method of re-routing an interconnection array that incorporates identifying a victim net and at least two aggressor nets and crossing the aggressor nets so that sections of multiple aggressor nets are positioned parallel to and adjacent to the victim net in order to minimizes the impact of coupling capacitance on the victim net with minimal changes to the wiring environment.
摘要翻译：公开了用于电路的互连阵列的实施例。互连阵列包括被平行于和相邻于多个交叉侵入网络的部分定位的受害网络，从而最小化电路由于耦合电容而导致的延迟或假开关的暴露。还公开了一种重新路由互连阵列的相关联的方法的实施例，该互连阵列包括识别受害网和至少两个攻击者网并且横穿攻击网，使得多个攻击者网的部分平行于并邻近受害网以便最小化耦合电容对受害网络的影响，同时对接线环境进行最小的改变。

6. 发明授权

US06725439B1 Method of automated design and checking for ESD robustness 有权
标题翻译：自动设计和检查ESD鲁棒性的方法
公开(公告)号：US06725439B1
公开(公告)日：2004-04-20
申请号：US09678742
申请日：2000-10-04
申请人： Philip S. Homsinger , Andrew D. Huber , Debra K. Korejwa , William J. Livingstone , Jeannie H. Panner , Erich C. Schanzenbach , Douglas W. Stout , Steven H. Voldman , Paul S. Zuchowski
发明人： Philip S. Homsinger , Andrew D. Huber , Debra K. Korejwa , William J. Livingstone , Jeannie H. Panner , Erich C. Schanzenbach , Douglas W. Stout , Steven H. Voldman , Paul S. Zuchowski
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5077
摘要： A integrated circuit (IC) chip with ESD robustness and the system and method of wiring the IC chip. Minimum wire width and maximum resistance constraints are applied to each of the chip's I/O ports. These constraints are propagated to the design. Array pads are wired to I/O cells located on the chip. Unused or floating pads may be tied to a power supply or ground line, either directly or through an electrostatic discharge (ESD) protect device. A multi-supply protect device (ESDxx) coupled between pairs of supplies and ground or to return lines is also included. Thus, wiring is such that wires and vias to ESD protect devices are wide enough to provide adequate ESD protection. Robust ESD protection is afforded all chip pads. The design may then be verified.
摘要翻译：具有ESD稳健性的集成电路（IC）芯片和IC芯片接线的系统和方法。每个芯片的I / O端口都应用最小导线宽度和最大电阻约束。这些限制被传播到设计中。阵列焊盘连接到位于芯片上的I / O单元。未使用或浮动焊盘可以直接或通过静电放电（ESD）保护装置连接到电源或接地线。还包括耦合在电源和接地或返回线路之间的多电源保护装置（ESDxx）。因此，布线使得ESD保护器件的导线和通孔足够宽，以提供足够的ESD保护。所有的芯片垫都提供了强大的ESD保护。然后可以验证设计。

7. 发明申请

US20090037857A1 METHODS FOR DESIGN RULE CHECKING WITH ABSTRACTED VIA OBSTRUCTIONS 有权
标题翻译：用于通过障碍物进行设计规则检查的方法
公开(公告)号：US20090037857A1
公开(公告)日：2009-02-05
申请号：US11830255
申请日：2007-07-30
申请人： Laura R. Darden , William J. Livingstone
发明人： Laura R. Darden , William J. Livingstone
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Methods of treating via obstructions during design rule checking. The method comprises examining the size of the via obstruction with respect to a minimum size and a minimum spacing constraint of a design rule. Based upon the comparison, a neighboring via count for a number of via shapes neighboring the via obstruction may be initialized to equal a positive integer. Based upon the comparison, the via obstruction may be represented with a plurality of smaller via shapes during design rule checking.
摘要翻译：在设计规则检查过程中通过障碍物进行治疗的方法。该方法包括相对于设计规则的最小尺寸和最小间距约束检查通孔阻塞的尺寸。基于比较，可以将与通孔阻塞相邻的多个通孔形状的相邻通孔计数初始化为等于正整数。基于比较，在设计规则检查期间，可以用多个较小的通孔形状来表示通孔阻塞。

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