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1. 发明申请

US20120216018A1 PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA 失效
公开(公告)号：US20120216018A1
公开(公告)日：2012-08-23
申请号：US13456761
申请日：2012-04-26
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F15/76 , G06F9/302
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

2. 发明授权

US07509367B2 Method and apparatus for performing multiply-add operations on packed data 有权
公开(公告)号：US07509367B2
公开(公告)日：2009-03-24
申请号：US10861167
申请日：2004-06-04
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

3. 发明授权

US06385634B1 Method for performing multiply-add operations on packed data 失效
标题翻译：对打包数据进行乘法运算的方法
公开(公告)号：US06385634B1
公开(公告)日：2002-05-07
申请号：US08522067
申请日：1995-08-31
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F738
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.
摘要翻译：一种用于在处理器中包括用于对压缩数据进行乘法运算的指令的方法和装置。在一个实施例中，处理器耦合到存储器。存储器中存储有第一打包数据和第二打包数据。处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。该第三打包数据中的至少两个数据元素存储对第一和第二打包数据中的数据元素执行加法运算的结果。

4. 发明授权

US07149882B2 Processor with instructions that operate on different data types stored in the same single logical register file 有权
标题翻译：处理器具有对存储在同一个逻辑寄存器文件中的不同数据类型进行操作的指令
公开(公告)号：US07149882B2
公开(公告)日：2006-12-12
申请号：US10844606
申请日：2004-05-11
申请人： Andrew F. Glew , Larry M. Mennemeier , Alexander D. Peleg , David Bistry , Millind Mittal , Carole Dulong , Eiichi Kowashi , Benny Eitan , Derrik Lin , Romamohan R. Vakkalagadda
发明人： Andrew F. Glew , Larry M. Mennemeier , Alexander D. Peleg , David Bistry , Millind Mittal , Carole Dulong , Eiichi Kowashi , Benny Eitan , Derrik Lin , Romamohan R. Vakkalagadda
IPC分类号： G06F7/38
CPC分类号： G06F9/3017 , G06F9/30036 , G06F9/30105 , G06F9/30109 , G06F9/30112 , G06F9/30134 , G06F9/30189 , G06F9/384 , G06F9/462
摘要： A processor with instructions to operate on different data types stored in a single logical register file. According to one embodiment of the invention, a processor includes a number of physical registers, a memory unit, and a decode/execution unit. The memory unit is to make the number of physical registers appear to software as a single software-visible register file. The decode/execution unit is to execute on the contents of the single software-visible register file instructions of a first instruction type and of a second instruction type, wherein the single software-visible register file is to be operated as a flat register file during execution of instructions of the second instruction type and as a stack referenced register file during execution of instructions of the first instruction type.
摘要翻译：具有对存储在单个逻辑寄存器文件中的不同数据类型进行操作的指令的处理器。根据本发明的一个实施例，处理器包括多个物理寄存器，存储器单元和解码/执行单元。存储单元是将物理寄存器的数量作为单个软件可见的寄存器文件显示在软件上。解码/执行单元执行第一指令类型和第二指令类型的单个软件可见寄存器文件指令的内容，其中单个软件可见寄存器文件将作为平坦寄存器文件操作在执行第一指令类型的指令期间执行第二指令类型的指令和作为堆栈引用的寄存器堆栈。

5. 发明授权

US5852726A Method and apparatus for executing two types of instructions that specify registers of a shared logical register file in a stack and a non-stack referenced manner 失效
标题翻译：用于执行两种类型的指令的方法和装置，这些指令指定堆栈中的共享逻辑寄存器文件的寄存器和非堆栈引用的方式
公开(公告)号：US5852726A
公开(公告)日：1998-12-22
申请号：US574719
申请日：1995-12-19
申请人： Derrick Lin , Romamohan R. Vakkalagadda , Andrew F. Glew , Larry M. Mennemeier , Alexander D. Peleg , David Bistry , Millind Mittal , Carole Dulong , Eiichi Kowashi , Benny Eitan
发明人： Derrick Lin , Romamohan R. Vakkalagadda , Andrew F. Glew , Larry M. Mennemeier , Alexander D. Peleg , David Bistry , Millind Mittal , Carole Dulong , Eiichi Kowashi , Benny Eitan
IPC分类号： G06F7/00 , G06F9/30 , G06F9/305 , G06F9/34 , G06F9/38 , G06F9/455 , G06F9/46 , G06F9/48 , G06F9/00
CPC分类号： G06F9/30123 , G06F9/30036 , G06F9/30109 , G06F9/30134 , G06F9/3824 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A method and apparatus for executing floating point and packed data instructions using a single physical register file that is aliased. According to one aspect of the invention, a processor is provided that includes a decode unit, a mapping unit, and a storage unit. The decode unit is configured to decode instructions and their operands from at least one instruction set including at least a first and second set of instructions. The storage unit includes a physical register file. The mapping unit is configured to map operands used by the first set of instructions to the physical register file in a stack referenced manner. In addition, the mapping unit is configured to map operands used by the second set of instructions to the same physical register file in a non-stack reference manner.
摘要翻译：一种用于使用别名的单个物理寄存器文件执行浮点和打包数据指令的方法和装置。根据本发明的一个方面，提供一种包括解码单元，映射单元和存储单元的处理器。解码单元被配置为从包括至少第一和第二组指令的至少一个指令集解码指令及其操作数。存储单元包括物理寄存器文件。映射单元被配置为以堆栈引用的方式将由第一组指令使用的操作数映射到物理寄存器文件。此外，映射单元被配置为将第二组指令使用的操作数以非堆栈参考方式映射到相同的物理寄存器文件。

6. 发明授权

US5835748A Method for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file 失效
标题翻译：用于执行不同的指令集的方法，使得处理器对不同物理寄存器文件执行不同的数据类型操作，这些文件在软件上逻辑上显示为单个别名寄存器文件
公开(公告)号：US5835748A
公开(公告)日：1998-11-10
申请号：US575704
申请日：1995-12-19
申请人： Doron Orenstein , Ofri Wechsler , Millind Mittal , Andrew F. Glew , Larry M. Mennemeier , Alexander D. Peleg , David Bistry , Carole Dulong , Eiichi Kowashi , Benny Eitan , Derrick Lin , Ramamohan R. Vakkalagadda
发明人： Doron Orenstein , Ofri Wechsler , Millind Mittal , Andrew F. Glew , Larry M. Mennemeier , Alexander D. Peleg , David Bistry , Carole Dulong , Eiichi Kowashi , Benny Eitan , Derrick Lin , Ramamohan R. Vakkalagadda
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318 , G06F9/38 , G06F9/00 , G06F9/06
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/30105 , G06F9/30109 , G06F9/3012 , G06F9/3013 , G06F9/30134 , G06F9/30192 , G06F9/3861
摘要： A method and apparatus for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file. According to one aspect of the invention, a processor is provided that includes at least two physical register files--one for executing scalar data type operations and the other for executing packed data type operations. In addition, the processor includes a transition unit that is configured to cause the two physical register files to logically appear to software executing on the processor as a single logical register file.
摘要翻译：一种用于执行不同指令集的方法和装置，该方法和装置使处理器对不同的物理寄存器文件执行不同的数据类型操作，所述物理寄存器文件作为单个混叠寄存器文件逻辑上显示为软件。根据本发明的一个方面，提供一种包括至少两个物理寄存器文件的处理器，一个用于执行标量数据类型操作，另一个用于执行打包数据类型操作。另外，处理器还包括转移单元，其被配置为使两个物理寄存器文件逻辑地出现在处理器上执行的软件作为单个逻辑寄存器文件。

7. 发明申请

US20120331028A1 PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA 失效
标题翻译：用于在包装数据上执行多重添加操作的处理器
公开(公告)号：US20120331028A1
公开(公告)日：2012-12-27
申请号：US13603370
申请日：2012-09-04
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.
摘要翻译：一种用于在处理器中包括用于对压缩数据进行乘法运算的指令的方法和装置。在一个实施例中，处理器耦合到存储器。存储器中存储有第一打包数据和第二打包数据。处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。该第三打包数据中的至少两个数据元素存储对第一和第二打包数据中的数据元素执行加法运算的结果。

8. 发明授权

US08185571B2 Processor for performing multiply-add operations on packed data 有权
标题翻译：用于对打包数据执行加法运算的处理器
公开(公告)号：US08185571B2
公开(公告)日：2012-05-22
申请号：US12409275
申请日：2009-03-23
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.
摘要翻译：一种用于在处理器中包括用于对压缩数据进行乘法运算的指令的方法和装置。在一个实施例中，处理器耦合到存储器。存储器中存储有第一打包数据和第二打包数据。处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。该第三打包数据中的至少两个数据元素存储对第一和第二打包数据中的数据元素执行加法运算的结果。

9. 发明授权

US07424505B2 Method and apparatus for performing multiply-add operations on packed data 有权
公开(公告)号：US07424505B2
公开(公告)日：2008-09-09
申请号：US09989736
申请日：2001-11-19
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

10. 发明授权

US5984515A Computer implemented method for providing a two dimensional rotation of packed data 失效
标题翻译：用于提供打包数据的二维旋转的计算机实现的方法
公开(公告)号：US5984515A
公开(公告)日：1999-11-16
申请号：US917671
申请日：1997-08-21
申请人： Larry M. Mennemeier , Alexander D. Peleg , Carole Dulong , Eiichi Kowashi , Millind Mittal , Benny Eitan
发明人： Larry M. Mennemeier , Alexander D. Peleg , Carole Dulong , Eiichi Kowashi , Millind Mittal , Benny Eitan
IPC分类号： G06F9/302 , G06T3/60 , G06F17/14
CPC分类号： G06F9/30014 , G06F9/30036 , G06T3/60
摘要： In a computer system having stored therein a first and a second packed data having corresponding data elements, a method for generating a two dimensional rotation of said packed data. The method includes the steps of generating a first set of intermediate results in response to a first instruction by multiplying the data elements of the first packed data with corresponding elements of a third packed data. The elements of said third packed data represent either a sine or cosine function. A second step of generating a second set of intermediate results in response to a second instruction by multiplying the data elements of the second packed data with corresponding elements of a fourth packed data. The elements of the fourth packed data represent either a sine or cosine function. A third and final step of generating a set of final results in response to a third instruction by performing an arithmetic operation between corresponding elements of the first and second sets of intermediate results. The final results represent a two dimensional rotation of the elements of the first set of packed data.
摘要翻译：在其中存储有具有相应数据元素的第一和第二打包数据的计算机系统中，一种用于产生所述打包数据的二维旋转的方法。该方法包括以下步骤：通过将第一打包数据的数据元素与第三打包数据的相应元素相乘来响应于第一指令来生成第一组中间结果。所述第三打包数据的元素表示正弦或余弦函数。第二步骤，通过将第二打包数据的数据元素与第四打包数据的对应元素相乘来响应于第二指令来生成第二组中间结果。第四打包数据的元素表示正弦或余弦函数。通过在第一和第二组中间结果的相应元素之间执行算术运算来产生响应于第三指令的一组最终结果的第三和最后一步骤。最终结果表示第一组打包数据的元素的二维旋转。

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