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1. 发明授权

US5852726A Method and apparatus for executing two types of instructions that specify registers of a shared logical register file in a stack and a non-stack referenced manner 失效
标题翻译：用于执行两种类型的指令的方法和装置，这些指令指定堆栈中的共享逻辑寄存器文件的寄存器和非堆栈引用的方式
公开(公告)号：US5852726A
公开(公告)日：1998-12-22
申请号：US574719
申请日：1995-12-19
申请人： Derrick Lin , Romamohan R. Vakkalagadda , Andrew F. Glew , Larry M. Mennemeier , Alexander D. Peleg , David Bistry , Millind Mittal , Carole Dulong , Eiichi Kowashi , Benny Eitan
发明人： Derrick Lin , Romamohan R. Vakkalagadda , Andrew F. Glew , Larry M. Mennemeier , Alexander D. Peleg , David Bistry , Millind Mittal , Carole Dulong , Eiichi Kowashi , Benny Eitan
IPC分类号： G06F7/00 , G06F9/30 , G06F9/305 , G06F9/34 , G06F9/38 , G06F9/455 , G06F9/46 , G06F9/48 , G06F9/00
CPC分类号： G06F9/30123 , G06F9/30036 , G06F9/30109 , G06F9/30134 , G06F9/3824 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A method and apparatus for executing floating point and packed data instructions using a single physical register file that is aliased. According to one aspect of the invention, a processor is provided that includes a decode unit, a mapping unit, and a storage unit. The decode unit is configured to decode instructions and their operands from at least one instruction set including at least a first and second set of instructions. The storage unit includes a physical register file. The mapping unit is configured to map operands used by the first set of instructions to the physical register file in a stack referenced manner. In addition, the mapping unit is configured to map operands used by the second set of instructions to the same physical register file in a non-stack reference manner.
摘要翻译：一种用于使用别名的单个物理寄存器文件执行浮点和打包数据指令的方法和装置。根据本发明的一个方面，提供一种包括解码单元，映射单元和存储单元的处理器。解码单元被配置为从包括至少第一和第二组指令的至少一个指令集解码指令及其操作数。存储单元包括物理寄存器文件。映射单元被配置为以堆栈引用的方式将由第一组指令使用的操作数映射到物理寄存器文件。此外，映射单元被配置为将第二组指令使用的操作数以非堆栈参考方式映射到相同的物理寄存器文件。

2. 发明授权

US06170997B2 Method for executing instructions that operate on different data types stored in the same single logical register file 失效
标题翻译：用于执行对存储在同一单个逻辑寄存器文件中的不同数据类型进行操作的指令的方法
公开(公告)号：US06170997B2
公开(公告)日：2001-01-09
申请号：US08898720
申请日：1997-07-22
申请人： Andrew F. Glew , Larry M. Mennemeier , Alexander D. Peleg , David Bistry , Millind Mittal , Carole Dulong , Eiichi Kowashi , Benny Eitan , Derrik Lin , Romamohan R. Vakkalagadda
发明人： Andrew F. Glew , Larry M. Mennemeier , Alexander D. Peleg , David Bistry , Millind Mittal , Carole Dulong , Eiichi Kowashi , Benny Eitan , Derrik Lin , Romamohan R. Vakkalagadda
IPC分类号： G06F9302
CPC分类号： G06F9/3017 , G06F9/30036 , G06F9/30101 , G06F9/30105 , G06F9/30109 , G06F9/30112 , G06F9/30134 , G06F9/30189 , G06F9/384 , G06F9/45533 , G06F9/462
摘要： A method for executing different sets of instructions that cause a processor to perform different data type operations in a manner that is invisible to various operating system techniques, that promotes good programming practices, and that is invisible to existing software conventions. According to one aspect of the invention, a data processing apparatus executes a first set of instructions of a first instruction type on what at least logically appears to software as a single logical register file. While the data processing apparatus is executing the first set of instructions, the single logical register file appears to be operated as a flat register file. In addition, the data processing apparatus executes a first instruction of a second instruction type using the logical register file. However, while the data processing apparatus is executing the first instruction, the logical register file appears to be operated as a stack referenced register file. Furthermore, the data processing apparatus alters all tags in a set of tags corresponding to the single logical register file to a non-empty state sometime between starting the execution of the first set of instructions and completing the execution of the first instruction. The tags identifying whether registers in the single logical register file are empty or non-empty.
摘要翻译：一种用于执行不同的指令集的方法，其使得处理器以对于各种操作系统技术是不可见的方式执行不同的数据类型操作，其促进良好的编程实践，并且对于现有的软件约定是不可见的。根据本发明的一个方面，数据处理设备执行第一指令类型的第一组指令，至少在软件上逻辑上显示为单个逻辑寄存器文件。当数据处理装置正在执行第一组指令时，单个逻辑寄存器文件似乎被操作为平坦寄存器文件。此外，数据处理装置使用逻辑寄存器文件执行第二指令类型的第一指令。然而，当数据处理装置正在执行第一指令时，逻辑寄存器文件似乎被操作为堆栈引用的寄存器文件。此外，在开始执行第一组指令并完成第一指令的执行之前的某个时刻，数据处理装置将对应于单个逻辑寄存器文件的一组标签中的所有标签改变为非空状态。识别单个逻辑寄存器文件中的寄存器是空还是非空的标签。

3. 发明授权

US07149882B2 Processor with instructions that operate on different data types stored in the same single logical register file 有权
标题翻译：处理器具有对存储在同一个逻辑寄存器文件中的不同数据类型进行操作的指令
公开(公告)号：US07149882B2
公开(公告)日：2006-12-12
申请号：US10844606
申请日：2004-05-11
申请人： Andrew F. Glew , Larry M. Mennemeier , Alexander D. Peleg , David Bistry , Millind Mittal , Carole Dulong , Eiichi Kowashi , Benny Eitan , Derrik Lin , Romamohan R. Vakkalagadda
发明人： Andrew F. Glew , Larry M. Mennemeier , Alexander D. Peleg , David Bistry , Millind Mittal , Carole Dulong , Eiichi Kowashi , Benny Eitan , Derrik Lin , Romamohan R. Vakkalagadda
IPC分类号： G06F7/38
CPC分类号： G06F9/3017 , G06F9/30036 , G06F9/30105 , G06F9/30109 , G06F9/30112 , G06F9/30134 , G06F9/30189 , G06F9/384 , G06F9/462
摘要： A processor with instructions to operate on different data types stored in a single logical register file. According to one embodiment of the invention, a processor includes a number of physical registers, a memory unit, and a decode/execution unit. The memory unit is to make the number of physical registers appear to software as a single software-visible register file. The decode/execution unit is to execute on the contents of the single software-visible register file instructions of a first instruction type and of a second instruction type, wherein the single software-visible register file is to be operated as a flat register file during execution of instructions of the second instruction type and as a stack referenced register file during execution of instructions of the first instruction type.
摘要翻译：具有对存储在单个逻辑寄存器文件中的不同数据类型进行操作的指令的处理器。根据本发明的一个实施例，处理器包括多个物理寄存器，存储器单元和解码/执行单元。存储单元是将物理寄存器的数量作为单个软件可见的寄存器文件显示在软件上。解码/执行单元执行第一指令类型和第二指令类型的单个软件可见寄存器文件指令的内容，其中单个软件可见寄存器文件将作为平坦寄存器文件操作在执行第一指令类型的指令期间执行第二指令类型的指令和作为堆栈引用的寄存器堆栈。

4. 发明授权

US5835748A Method for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file 失效
标题翻译：用于执行不同的指令集的方法，使得处理器对不同物理寄存器文件执行不同的数据类型操作，这些文件在软件上逻辑上显示为单个别名寄存器文件
公开(公告)号：US5835748A
公开(公告)日：1998-11-10
申请号：US575704
申请日：1995-12-19
申请人： Doron Orenstein , Ofri Wechsler , Millind Mittal , Andrew F. Glew , Larry M. Mennemeier , Alexander D. Peleg , David Bistry , Carole Dulong , Eiichi Kowashi , Benny Eitan , Derrick Lin , Ramamohan R. Vakkalagadda
发明人： Doron Orenstein , Ofri Wechsler , Millind Mittal , Andrew F. Glew , Larry M. Mennemeier , Alexander D. Peleg , David Bistry , Carole Dulong , Eiichi Kowashi , Benny Eitan , Derrick Lin , Ramamohan R. Vakkalagadda
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318 , G06F9/38 , G06F9/00 , G06F9/06
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/30105 , G06F9/30109 , G06F9/3012 , G06F9/3013 , G06F9/30134 , G06F9/30192 , G06F9/3861
摘要： A method and apparatus for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file. According to one aspect of the invention, a processor is provided that includes at least two physical register files--one for executing scalar data type operations and the other for executing packed data type operations. In addition, the processor includes a transition unit that is configured to cause the two physical register files to logically appear to software executing on the processor as a single logical register file.
摘要翻译：一种用于执行不同指令集的方法和装置，该方法和装置使处理器对不同的物理寄存器文件执行不同的数据类型操作，所述物理寄存器文件作为单个混叠寄存器文件逻辑上显示为软件。根据本发明的一个方面，提供一种包括至少两个物理寄存器文件的处理器，一个用于执行标量数据类型操作，另一个用于执行打包数据类型操作。另外，处理器还包括转移单元，其被配置为使两个物理寄存器文件逻辑地出现在处理器上执行的软件作为单个逻辑寄存器文件。

5. 发明授权

US5701508A Executing different instructions that cause different data type operations to be performed on single logical register file 失效
标题翻译：执行导致在单个逻辑寄存器文件上执行不同数据类型操作的不同指令
公开(公告)号：US5701508A
公开(公告)日：1997-12-23
申请号：US574500
申请日：1995-12-19
申请人： Andrew F. Glew , Larry M. Mennemeier , Alexander D. Peleg , David Bistry , Millind Mittal , Carole Dulong , Eiichi Kowashi , Benny Eitan , Derrick Lin , Ramamohan R. Vakkalagadda
发明人： Andrew F. Glew , Larry M. Mennemeier , Alexander D. Peleg , David Bistry , Millind Mittal , Carole Dulong , Eiichi Kowashi , Benny Eitan , Derrick Lin , Ramamohan R. Vakkalagadda
IPC分类号： G06F9/30 , G06F9/318 , G06F9/455 , G06F9/46 , G06F9/00
CPC分类号： G06F9/3017 , G06F9/30036 , G06F9/30101 , G06F9/30105 , G06F9/30109 , G06F9/30112 , G06F9/30134 , G06F9/30189 , G06F9/384 , G06F9/45533 , G06F9/462
摘要： A method for executing different sets of instructions that cause a processor to perform different data type operations in a manner that is invisible to various operating system techniques, that promotes good programming practices, and that is invisible to existing software conventions. According to one aspect of the invention, a data processing apparatus executes a first set of instructions of a first instruction type on what at least logically appears to software as a single logical register file. While the data processing apparatus is executing the first set of instructions, the single logical register file appears to be operated as a flat register file. In addition, the data processing apparatus executes a first instruction of a second instruction type using the logical register file. However, while the data processing apparatus is executing the first instruction, the logical register file appears to be operated as a stack referenced register file. Furthermore, the data processing apparatus alters all tags in a set of tags corresponding to the single logical register file to a non-empty state sometime between starting the execution of the first set of instructions and completing the execution of the first instruction. The tags identifying whether registers in the single logical register file are empty or non-empty.
摘要翻译：一种用于执行不同的指令集的方法，其使得处理器以对于各种操作系统技术是不可见的方式执行不同的数据类型操作，其促进良好的编程实践，并且对于现有的软件约定是不可见的。根据本发明的一个方面，数据处理设备执行第一指令类型的第一组指令，至少在软件上逻辑上显示为单个逻辑寄存器文件。当数据处理装置正在执行第一组指令时，单个逻辑寄存器文件似乎被操作为平坦寄存器文件。此外，数据处理装置使用逻辑寄存器文件执行第二指令类型的第一指令。然而，当数据处理装置正在执行第一指令时，逻辑寄存器文件似乎被操作为堆栈引用的寄存器文件。此外，在开始执行第一组指令并完成第一指令的执行之前的某个时刻，数据处理装置将对应于单个逻辑寄存器文件的一组标签中的所有标签改变为非空状态。识别单个逻辑寄存器文件中的寄存器是空还是非空的标签。

6. 发明授权

US06792523B1 Processor with instructions that operate on different data types stored in the same single logical register file 失效
标题翻译：处理器具有对存储在同一个逻辑寄存器文件中的不同数据类型进行操作的指令
公开(公告)号：US06792523B1
公开(公告)日：2004-09-14
申请号：US09363116
申请日：1999-07-27
申请人： Andrew F. Glew , Larry M. Menneneier , Alexander D. Peleg , David Bistry , Millind Mittal , Carole Dulong , Eiichi Kowashi , Benny Eitan , Derrik Lin , Romamohan R. Vakkalagadda
发明人： Andrew F. Glew , Larry M. Menneneier , Alexander D. Peleg , David Bistry , Millind Mittal , Carole Dulong , Eiichi Kowashi , Benny Eitan , Derrik Lin , Romamohan R. Vakkalagadda
IPC分类号： G06F1200
CPC分类号： G06F9/3017 , G06F9/30036 , G06F9/30105 , G06F9/30109 , G06F9/30112 , G06F9/30134 , G06F9/30189 , G06F9/384 , G06F9/462
摘要： A processor with instructions to operate on different data types stored in a single logical register file. According to one aspect of the invention, a first set of instructions of a first instruction type operates on the contents of what at least logically appears to software as a single logical register file. The first set of instructions appears to access the single logical register file as a flat register file. In addition, a first instruction of a second instruction type operates on the logical register file. However, the first instruction appears to access the logical register file as a stack referenced register file. Furthermore, sometime between starting the execution of the first set of instructions and completing the execution of the first instruction, all tags in a set of tags indicating whether corresponding registers in the single logical register file are empty or non-empty are caused to indicate non-empty states.
摘要翻译：具有对存储在单个逻辑寄存器文件中的不同数据类型进行操作的指令的处理器。根据本发明的一个方面，第一指令类型的第一组指令对至少逻辑上显示为软件的内容进行操作，作为单个逻辑寄存器文件。第一组指令似乎以平坦寄存器文件的形式访问单个逻辑寄存器文件。此外，第二指令类型的第一指令对逻辑寄存器文件进行操作。但是，第一条指令似乎以堆栈引用的寄存器文件的形式访问逻辑寄存器文件。此外，在开始第一组指令的执行和完成第一指令的执行之间的某个时刻，引起一组标签中指示单个逻辑寄存器文件中的相应寄存器是空还是非空的所有标签，空状态。

7. 发明授权

US5935240A Computer implemented method for transferring packed data between register files and memory 失效
标题翻译：用于在寄存器文件和存储器之间传送打包数据的计算机实现的方法
公开(公告)号：US5935240A
公开(公告)日：1999-08-10
申请号：US573238
申请日：1995-12-15
申请人： Larry M. Mennemeier , Alexander D. Peleg , Andrew F. Glew , Carole Dulong , Eiichi Kowashi , Millind Mittal , Wolf Witt , Benny Eitan
发明人： Larry M. Mennemeier , Alexander D. Peleg , Andrew F. Glew , Carole Dulong , Eiichi Kowashi , Millind Mittal , Wolf Witt , Benny Eitan
IPC分类号： G06F13/16 , G06F9/305
CPC分类号： G06F13/16
摘要： A method for transferring packed data including the steps of first receiving an instruction from a set of instructions for transferring packed data between an extended register file and either an integer register file or a memory. In one embodiment, the extended register file includes eight registers, with each of the extended register storing up to sixty-four data bits. The integer register file also includes eight registers. The instruction includes an opcode that specifies a direction of the transfer with respect to the extended register file. The instructions are encoded in an instruction format having up to three bits addressing a destination operand and up to three bits addressing a source operand. The instruction is then translated to determine a direction of the transfer, a size of said packed data to be transferred, the address of the destination operand, and the address of the source operand. The instruction decoded by a decoder unit previously designed to decode the instruction format used to encode the set of instructions. In response to receiving the instruction, the packed data is transferred between the extended register file and either the integer register file or the memory, pursuant to the specifications of the translated instruction.
摘要翻译：一种用于传送打包数据的方法，包括以下步骤：首先从扩展寄存器文件和整数寄存器文件或存储器之间传送打包数据的一组指令接收指令。在一个实施例中，扩展寄存器文件包括八个寄存器，每个扩展寄存器最多存储64个数据位。整数寄存器文件还包括八个寄存器。该指令包括指定关于扩展寄存器文件的传送方向的操作码。指令以指令格式进行编码，最多三位寻址目标操作数，最多三位寻址源操作数。然后转换该指令以确定传送的方向，要传送的所述打包数据的大小，目的地操作数的地址和源操作数的地址。由解码器单元解码的指令，其先前设计为解码用于编码指令集的指令格式。响应于接收到该指令，根据翻译指令的规范，打包数据在扩展寄存器文件和整数寄存器文件或存储器之间传送。

8. 发明申请

US20120216018A1 PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA 失效
公开(公告)号：US20120216018A1
公开(公告)日：2012-08-23
申请号：US13456761
申请日：2012-04-26
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F15/76 , G06F9/302
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

9. 发明授权

US07509367B2 Method and apparatus for performing multiply-add operations on packed data 有权
公开(公告)号：US07509367B2
公开(公告)日：2009-03-24
申请号：US10861167
申请日：2004-06-04
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

10. 发明授权

US06385634B1 Method for performing multiply-add operations on packed data 失效
标题翻译：对打包数据进行乘法运算的方法
公开(公告)号：US06385634B1
公开(公告)日：2002-05-07
申请号：US08522067
申请日：1995-08-31
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F738
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.
摘要翻译：一种用于在处理器中包括用于对压缩数据进行乘法运算的指令的方法和装置。在一个实施例中，处理器耦合到存储器。存储器中存储有第一打包数据和第二打包数据。处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。该第三打包数据中的至少两个数据元素存储对第一和第二打包数据中的数据元素执行加法运算的结果。

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