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1. 发明授权

US09304535B2 Baud rate phase detector with no error latches 有权
标题翻译：波特率相位检测器，无错误锁存
公开(公告)号：US09304535B2
公开(公告)日：2016-04-05
申请号：US14222157
申请日：2014-03-21
申请人： LSI Corporation
发明人： Volodymyr Shvydun , Adam B. Healey , Chaitanya Palusa , Hiep T. Pham
IPC分类号： G06F1/12 , G06F7/00 , H04L7/033 , H04L27/26 , H03L7/091 , H04L27/227 , H04L27/00 , H04L27/06 , H04L25/02 , H03L7/087
CPC分类号： G06F1/12 , H03L7/087 , H03L7/091 , H04L7/0338 , H04L25/022 , H04L27/066 , H04L27/2275 , H04L27/2695 , H04L2027/0067
摘要： Phase detectors and timing recovery techniques that do not require error latches nor oversampling of the received input data are disclosed. The phase detection method includes separating an input signal into N consecutive data bits; comparing at least two consecutive data bits within the N consecutive data bits; estimating a data bit value for each of the N consecutive data bits; and determining a phase difference based on a data bit pattern formed by the data bit values of the N consecutive data bits and the comparison of the at least two consecutive data bits within the N consecutive data bits.
摘要翻译：公开了不需要错误锁存器或接收的输入数据的过采样的相位检测器和定时恢复技术。相位检测方法包括将输入信号分离成N个连续数据位; 比较N个连续数据比特中的至少两个连续数据比特; 估计每个N个连续数据比特的数据比特值; 以及基于由N个连续数据位的数据位值形成的数据位模式和在N个连续数据位中的至少两个连续数据位的比较来确定相位差。

2. 发明授权

US09036729B2 Code forwarding and clock generation for transmitter repeaters 有权
标题翻译：发射机中继器的代码转发和时钟生成
公开(公告)号：US09036729B2
公开(公告)日：2015-05-19
申请号：US13873003
申请日：2013-04-29
申请人： LSI Corporation
发明人： Hiep Pham , Chaitanya Palusa , Tomasz Prokop , Adam Healey
IPC分类号： H04L7/00 , H04L27/12 , H03L7/06 , H03L7/08 , H04L7/027 , H03L7/099
CPC分类号： H04L27/122 , H03L7/06 , H03L7/0807 , H03L7/0998 , H04L7/0012 , H04L7/0016 , H04L7/0025 , H04L7/0029 , H04L7/027
摘要： A repeater includes a clock-and-data recovery element and a phase interpolator to extract an embedded clock frequency from a data stream. The phase interpolator determine a frequency offset and sends such offset as phase interpolator codes to a filter and scaler. The filtered, scaled phase interpolator codes are used to produce a reference clock frequency for retransmission.
摘要翻译：中继器包括时钟和数据恢复元件以及从数据流提取嵌入式时钟频率的相位内插器。相位插值器确定频率偏移，并将相位内插器码的偏移发送到滤波器和缩放器。滤波的，缩放的相位内插器码用于产生用于重传的参考时钟频率。

3. 发明授权

US08804889B2 Receiver with dual clock recovery circuits 有权
标题翻译：具有双时钟恢复电路的接收器
公开(公告)号：US08804889B2
公开(公告)日：2014-08-12
申请号：US13738185
申请日：2013-01-10
申请人： LSI Corporation
发明人： Chaitanya Palusa , Tomasz Prokop
IPC分类号： H04L7/00 , H04L27/38 , H04L27/06 , H03D3/24
CPC分类号： H04L7/0087 , H04L7/0037 , H04L7/033 , H04L7/0337
摘要： A receiver derives the desired data sampling clock phase by averaging the phase information of transitions before and after a data eye. The average of the phase information reduces data clock phase error due to variations in the phases of transitions in received data signals depending on the polarity and positions of the transitions.
摘要翻译：接收器通过对数据眼前后的转换的相位信息进行平均来得出期望的数据采样时钟相位。相位信息的平均值由于接收数据信号中的转变的相位的变化而减小数据时钟相位误差，这取决于转换的极性和位置。

4. 发明授权

US09385893B2 Modular low power serializer-deserializer 有权
标题翻译：模块化低功率串行器 - 解串器
公开(公告)号：US09385893B2
公开(公告)日：2016-07-05
申请号：US14176728
申请日：2014-02-10
申请人： LSI Corporation
发明人： Chaitanya Palusa , Tomasz Prokop , Hiep T. Pham , Volodymyr Shvydun , Adam B. Healey
IPC分类号： H04B1/38 , H04L5/16 , H04L27/10 , H04L27/18 , H04L25/03 , H04L7/00 , H04L27/00 , H04L7/02 , H03M1/12 , H03M1/38
CPC分类号： H04L25/03057 , H03M1/1215 , H03M1/38 , H04L7/0087 , H04L7/02 , H04L25/03 , H04L27/0002
摘要： Modular, low power serializer-deserializer receivers and methods for configuring such receivers are disclosed. The disclosed receivers are configured to sample input signals at the front-end utilizing a plurality of track-and-hold circuits time-interleaved based on a plurality of phase-shifted clock signals. The disclosed receivers are also modular and various processing components, including analog front-end and equalizers, are selectively utilized based on the determined length of the communication channel, ranging from ultra short reach applications to very short reach, medium reach, long reach and extra long reach applications.
摘要翻译：公开了模块化的低功率串行器 - 解串器接收器和用于配置这种接收器的方法。所公开的接收机被配置为利用基于多个相移时钟信号时间交织的多个跟踪和保持电路来采样前端的输入信号。所公开的接收机也是模块化的，并且基于确定的通信信道长度有选择地使用包括模拟前端和均衡器的各种处理组件，从超短距离应用到非常短的范围，中等到达，长距离和额外的长期应用。

5. 发明授权

US09215106B2 Method and apparatus for pre-cursor intersymbol interference correction 有权
标题翻译：前置符号间干扰校正的方法和装置
公开(公告)号：US09215106B2
公开(公告)日：2015-12-15
申请号：US14221968
申请日：2014-03-21
申请人： LSI Corporation
发明人： Chaitanya Palusa , Adam B. Healey , Hiep T. Pham , Volodymyr Shvydun
IPC分类号： H04L25/03 , H03M1/00 , H04L1/06
CPC分类号： H04L25/03057 , H03H2218/06 , H03M1/00 , H03M1/14 , H03M2201/4135 , H04L1/06
摘要： A multi-stage system and method for correcting intersymbol interference is disclosed. The system includes a first estimation module configured to sample an input signal to produce a first set of estimated data bits. The system also includes a second estimation module configured to sample the input signal phase shifted by a predetermined phase shift unit to produce a second set of estimated data bits, wherein the second set of estimated data bits are produced at least partially based on the first set of estimated data bits and at least one pre-cursor coefficient.
摘要翻译：公开了一种用于校正码间干扰的多级系统和方法。该系统包括被配置为对输入信号进行采样以产生第一组估计数据位的第一估计模块。该系统还包括第二估计模块，其被配置为对由预定相移单元移位的输入信号相位进行采样以产生第二组估计数据位，其中第二组估计数据位至少部分地基于第一组产生的估计数据位和至少一个前置标准系数。

6. 发明授权

US09130797B1 Pipelined decision feedback equalization in an interleaved serializer/deserializer receiver 有权
标题翻译：交错串行器/解串器接收器中的流水线判决反馈均衡
公开(公告)号：US09130797B1
公开(公告)日：2015-09-08
申请号：US14267568
申请日：2014-05-01
申请人： LSI Corporation
发明人： Chaitanya Palusa , Volodymyr Shvydun , Hiep T. Pham , Adam B. Healey
IPC分类号： H04B1/38 , H04L25/03
CPC分类号： H04L25/03878 , H04L25/03146
摘要： An interleaved track-and-hold front-end with multiphase clocks computes and propagates unrolled decision feedback equalization results along a pipeline with the final outputs selected from one of the interleaved previous output bits with a multiplexer operating over multiple unit intervals instead of one unit interval. An n-way interleaved serializer/deserializer utilizes an n unit interval multiplexer or n one unit interval multiplexers. Pipelined decision feedback equalization allows multiple, slower multiplexers.
摘要翻译：具有多相时钟的交错跟踪和保持前端计算并沿着流水线传播展开的判决反馈均衡结果，其中最终输出从交织的先前输出位之一中选择，多路复用器以多个单位间隔工作，而不是一个单位间隔。 n路交错串行器/解串器利用n单位间隔多路复用器或n个单位间隔多路复用器。流水线判决反馈均衡允许多个较慢的多路复用器。

7. 发明申请

US20150236875A1 Method and Apparatus for Pre-Cursor Intersymbol Interference Correction 有权
标题翻译：用于前置光标符号间干扰校正的方法和装置
公开(公告)号：US20150236875A1
公开(公告)日：2015-08-20
申请号：US14221968
申请日：2014-03-21
申请人： LSI Corporation
发明人： Chaitanya Palusa , Adam B. Healey , Hiep T. Pham , Volodymyr Shvydun
IPC分类号： H04L25/03
CPC分类号： H04L25/03057 , H03H2218/06 , H03M1/00 , H03M1/14 , H03M2201/4135 , H04L1/06
摘要： A multi-stage system and method for correcting intersymbol interference is disclosed. The system includes a first estimation module configured to sample an input signal to produce a first set of estimated data bits. The system also includes a second estimation module configured to sample the input signal phase shifted by a predetermined phase shift unit to produce a second set of estimated data bits, wherein the second set of estimated data bits are produced at least partially based on the first set of estimated data bits and at least one pre-cursor coefficient.
摘要翻译：公开了一种用于校正码间干扰的多级系统和方法。该系统包括被配置为对输入信号进行采样以产生第一组估计数据位的第一估计模块。该系统还包括第二估计模块，其被配置为对由预定相移单元移位的输入信号相位进行采样以产生第二组估计数据位，其中第二组估计数据位至少部分地基于第一组产生的估计数据位和至少一个前置标准系数。

8. 发明申请

US20150207648A1 Modular Low Power Serializer-Deserializer 有权
标题翻译：模块化低功耗串行器 - 解串器
公开(公告)号：US20150207648A1
公开(公告)日：2015-07-23
申请号：US14176728
申请日：2014-02-10
申请人： LSI Corporation
发明人： Chaitanya Palusa , Tomasz Prokop , Hiep T. Pham , Volodymyr Shvydun , Adam B. Healey
IPC分类号： H04L25/03 , H04L27/00 , H04L7/00
CPC分类号： H04L25/03057 , H03M1/1215 , H03M1/38 , H04L7/0087 , H04L7/02 , H04L25/03 , H04L27/0002
摘要： Modular, low power serializer-deserializer receivers and methods for configuring such receivers are disclosed. The disclosed receivers are configured to sample input signals at the front-end utilizing a plurality of track-and-hold circuits time-interleaved based on a plurality of phase-shifted clock signals. The disclosed receivers are also modular and various processing components, including analog front-end and equalizers, are selectively utilized based on the determined length of the communication channel, ranging from ultra short reach applications to very short reach, medium reach, long reach and extra long reach applications.
摘要翻译：公开了模块化的低功率串行器 - 解串器接收器和用于配置这种接收器的方法。所公开的接收机被配置为利用基于多个相移时钟信号时间交织的多个跟踪和保持电路来采样前端的输入信号。所公开的接收机也是模块化的，并且基于确定的通信信道长度有选择地使用包括模拟前端和均衡器的各种处理组件，从超短距离应用到非常短的范围，中等到达，长距离和额外的长期应用。

9. 发明申请

US20140233668A1 Code Forwarding and Clock Generation for Transmitter Repeaters 有权
标题翻译：发射机中继器的代码转发和时钟生成
公开(公告)号：US20140233668A1
公开(公告)日：2014-08-21
申请号：US13873003
申请日：2013-04-29
申请人： LSI CORPORATION
发明人： Hiep Pham , Chaitanya Palusa , Tomasz Prokop , Adam Healey
IPC分类号： H04L27/12
CPC分类号： H04L27/122 , H03L7/06 , H03L7/0807 , H03L7/0998 , H04L7/0012 , H04L7/0016 , H04L7/0025 , H04L7/0029 , H04L7/027
摘要： A repeater includes a clock-and-data recovery element and a phase interpolator to extract an embedded clock frequency from a data stream. The phase interpolator determine a frequency offset and sends such offset as phase interpolator codes to a filter and scaler. The filtered, scaled phase interpolator codes are used to produce a reference clock frequency for retransmission.
摘要翻译：中继器包括时钟和数据恢复元件以及从数据流提取嵌入式时钟频率的相位内插器。相位插值器确定频率偏移，并将相位内插器码的偏移发送到滤波器和缩放器。滤波的，缩放的相位内插器码用于产生用于重传的参考时钟频率。

10. 发明申请

US20150256363A1 Integrated PAM4/NRZ N-Way Parallel Digital Unrolled Decision Feedback Equalizer (DFE) 审中-公开
标题翻译：集成PAM4 / NRZ N路并行数字展开决策反馈均衡器（DFE）
公开(公告)号：US20150256363A1
公开(公告)日：2015-09-10
申请号：US14226915
申请日：2014-03-27
申请人： LSI Corporation
发明人： Volodymyr Shvydun , Adam B. Healey , Chaitanya Palusa
IPC分类号： H04L25/03 , H04L25/49
CPC分类号： H04L25/03057 , H04L25/4917 , H04L2025/03535
摘要： An N-way parallel, unrolled decision feedback equalizer for a SerDes receiver can convert between four-tap PAM-2 and two-tap PAM-4 mode, maximizing hardware through the use of mode control multiplexers. Each of N interleaved parallel branches includes an ISI correction stage for generating a partial result approximating intersymbol interference and comparing the partial result to a threshold, a carry look-ahead stage for generating a second partial result based in part on previously generated partial results, and a decision feedback stage for generating a final decision based on previous branches. Mode control multiplexers can select from PAM-2 and PAM-4 operating modes, PAM-2 and MAP-4 inputs at various stages, or from single-bit PAM-2 and two-bit PAM-4 outputs. ISI correction can additionally be reformulated to incorporate comparing raw input symbols to a combination of approximated ISI and a threshold.
摘要翻译：用于SerDes接收机的N路并行，展开的判决反馈均衡器可以在四抽头PAM-2和二抽头PAM-4模式之间进行转换，通过使用模式控制多路复用器最大化硬件。 N个交错并行分支中的每一个包括用于产生近似符号间干扰的部分结果和将部分结果与阈值进行比较的ISI校正级，部分地基于先前产生的部分结果来生成第二部分结果的进位预测级，以及用于根据先前分支产生最终决定的决策反馈阶段。模式控制多路复用器可以从PAM-2和PAM-4操作模式，PAM-2和MAP-4输入在各个阶段，或单位PAM-2和两位PAM-4输出中进行选择。 ISI校正可以另外被重新配置，以将原始输入符号与近似ISI和阈值的组合进行比较。

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