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1. 发明授权

US07835204B2 Semiconductor memory device for generating column address 有权
标题翻译：用于产生列地址的半导体存储器件
公开(公告)号：US07835204B2
公开(公告)日：2010-11-16
申请号：US12165030
申请日：2008-06-30
申请人： Kyung-Whan Kim , Eun-Young Park
发明人： Kyung-Whan Kim , Eun-Young Park
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C11/4076 , G11C11/408
摘要： A semiconductor memory device can ensure a sufficient margin between a column select signal and a column address signal when a delay time of the column select signal is increased to improve an address access time during a write operation. The semiconductor memory device includes a discrimination signal generating circuit configured to generate a discrimination signal activated in a write operation of the device, and a selective delay circuit configured to selectively delay a column address in response to the discrimination signal.
摘要翻译：当列选择信号的延迟时间增加以改善写入操作期间的地址访问时间时，半导体存储器件可以确保列选择信号和列地址信号之间的足够余量。半导体存储器件包括识别信号发生电路，其被配置为产生在器件的写入操作中激活的识别信号，以及选择延迟电路，被配置为响应于判别信号选择性地延迟列地址。

2. 发明申请

US20090168567A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090168567A1
公开(公告)日：2009-07-02
申请号：US12165030
申请日：2008-06-30
申请人： Kyung-Whan Kim , Eun-Young Park
发明人： Kyung-Whan Kim , Eun-Young Park
IPC分类号： G11C7/22
CPC分类号： G11C7/22 , G11C11/4076 , G11C11/408
摘要： A semiconductor memory device can ensure a sufficient margin between a column select signal and a column address signal when a delay time of the column select signal is increased to improve an address access time during a write operation. The semiconductor memory device includes a discrimination signal generating circuit configured to generate a discrimination signal activated in a write operation of the device, and a selective delay circuit configured to selectively delay a column address in response to the discrimination signal.
摘要翻译：当列选择信号的延迟时间增加以改善写入操作期间的地址访问时间时，半导体存储器件可以确保列选择信号和列地址信号之间的足够余量。半导体存储器件包括识别信号发生电路，其被配置为产生在器件的写入操作中激活的识别信号，以及选择延迟电路，被配置为响应于判别信号选择性地延迟列地址。

3. 发明授权

US07816941B2 Circuit and method for controlling termination impedance 有权
标题翻译：用于控制终端阻抗的电路和方法
公开(公告)号：US07816941B2
公开(公告)日：2010-10-19
申请号：US12215830
申请日：2008-06-30
申请人： Kyung-Whan Kim , Kyung-Hoon Kim
发明人： Kyung-Whan Kim , Kyung-Hoon Kim
IPC分类号： H03K17/16 , H03K19/003 , G11C7/00
CPC分类号： G11C5/063 , G11C7/1051 , G11C7/1057 , G11C2207/2254
摘要： A termination impedance control circuit is capable of controlling a dynamic ODT operation in a DDR3-level semiconductor memory device. The termination impedance control circuit includes a counter unit configured to count an external clock and an internal clock to output a first code and a second code, respectively, and a dynamic controller configured to enable a dynamic termination operation by comparing the first code with the second code in response to a write command and disable the dynamic termination operation after a predetermined time, determined according to a burst length, has lapsed after the dynamic termination operation is enabled.
摘要翻译：终端阻抗控制电路能够控制DDR3级半导体存储器件中的动态ODT操作。终端阻抗控制电路包括：计数器单元，被配置为对外部时钟和内部时钟进行计数，以分别输出第一代码和第二代码;以及动态控制器，被配置为通过将第一代码与第二代码进行比较来实现动态终止操作响应于写命令的代码，并且在启用了动态终止操作之后已经经过了在根据突发长度确定的预定时间之后禁用动态终止操作。

4. 发明授权

US07573771B2 High voltage generator and semiconductor memory device 失效
标题翻译：高压发生器和半导体存储器件
公开(公告)号：US07573771B2
公开(公告)日：2009-08-11
申请号：US11528531
申请日：2006-09-28
申请人： Kyung-Whan Kim
发明人： Kyung-Whan Kim
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C5/145 , G11C11/40611 , G11C11/40615 , G11C11/40618 , G11C11/4074 , G11C2211/4067 , G11C2211/4068
摘要： A high voltage generator includes: a high voltage detecting unit for detecting a level of a high voltage and outputting a high enable signal; an auto refresh control unit for enabling an auto refresh high enable signal in response to a detection signal enabled when a level of a power supplying voltage is lower than a certain level and in response to the pumping enable signal during an auto refresh operation; and a high voltage generating unit for generating a high voltage by performing a pumping operation in response to the auto refresh pumping enable signal.
摘要翻译：高电压发生器包括：高电压检测单元，用于检测高电平电平并输出高使能信号; 自动刷新控制单元，用于当电力供应电压的电平低于一定电平时响应于启用的检测信号，并且响应于在自动刷新操作期间的泵送使能信号，启用自动刷新高使能信号; 以及高电压产生单元，用于通过响应于自动刷新泵送使能信号执行泵浦操作来产生高电压。

5. 发明授权

US07016255B2 Multi-port memory device 有权
标题翻译：多端口存储设备
公开(公告)号：US07016255B2
公开(公告)日：2006-03-21
申请号：US10876231
申请日：2004-06-23
申请人： Ihl-Ho Lee , Kyung-Whan Kim , Jae-Jin Lee
发明人： Ihl-Ho Lee , Kyung-Whan Kim , Jae-Jin Lee
IPC分类号： G11C7/00
CPC分类号： G11C7/1075 , G11C8/16 , G11C11/4097 , G11C29/846 , G11C2207/002
摘要： A multi-port memory device can avoid failure of the first high data during initial operation so that reliability and operation characteristic of the memory device can be improved. The multi-port memory device comprises a global data bus having a multiplicity of bus lines, a plurality of banks having a current sensing type transceiving structure for exchanging data with the global data bus, one or more ports having a current sensing type transceiving structure for exchanging data with the global data bus, a plurality of switches, each arranged between the corresponding bank and the bus lines of the global data bus for selectively connecting one of a redundant column and normal columns of the corresponding bank to the global data bus, and a controlling unit for restricting the turn-on period of the switches to the substantial operation period of the corresponding bank.
摘要翻译：多端口存储器件可以避免初始操作期间第一高数据的故障，从而可以提高存储器件的可靠性和操作特性。多端口存储器件包括具有多条总线线路的全局数据总线，多个存储体具有用于与全局数据总线交换数据的电流检测型收发结构，具有电流检测型收发结构的一个或多个端口与全局数据总线交换数据，多个开关，每个交换机布置在全局数据总线的对应组和总线之间，用于选择性地将对应组的冗余列和正常列之一连接到全局数据总线;以及控制单元，用于将开关的导通周期限制到相应银行的实质操作周期。

6. 发明授权

US08559245B2 Internal voltage generating circuit having selectively driven drivers in semiconductor memory apparatus 有权
标题翻译：内部电压发生电路在半导体存储装置中具有选择性驱动的驱动器
公开(公告)号：US08559245B2
公开(公告)日：2013-10-15
申请号：US12331289
申请日：2008-12-09
申请人： Khil-Ohk Kang , Kyung-Whan Kim
发明人： Khil-Ohk Kang , Kyung-Whan Kim
IPC分类号： G11C7/12 , G11C8/08
CPC分类号： G11C5/147 , G11C11/4099
摘要： An internal voltage generating circuit of a semiconductor memory apparatus includes a first voltage generating unit to output a first output voltage to a common node, the first output voltage is generated in response to a first reference voltage, and a second voltage generating unit to output a second output voltage to the common node, the second output voltage is generated in response to a second reference voltage.
摘要翻译：半导体存储装置的内部电压产生电路包括：第一电压产生单元，用于向公共节点输出第一输出电压，响应于第一参考电压产生第一输出电压;以及第二电压产生单元，第二输出电压到公共节点，响应于第二参考电压产生第二输出电压。

7. 发明授权

US08248129B2 Signal delay circuit, clock transfer control circuit and semiconductor device having the same 有权
标题翻译：信号延迟电路，时钟传输控制电路和具有该信号的半导体器件
公开(公告)号：US08248129B2
公开(公告)日：2012-08-21
申请号：US12792530
申请日：2010-06-02
申请人： Hyoung-Jun Na , Kyung-Whan Kim
发明人： Hyoung-Jun Na , Kyung-Whan Kim
IPC分类号： H03K3/017
CPC分类号： H03K5/04
摘要： A signal delay circuit including a clock transfer control circuit configured to transmit or block a clock signal, and a pulse signal generation circuit configured to delay a first pulse signal in response to the transmitted clock signal to generate a second pulse signal which has a longer active period than the first pulse signal.
摘要翻译：一种信号延迟电路，包括被配置为发送或阻断时钟信号的时钟传送控制电路，以及脉冲信号生成电路，被配置为响应于发送的时钟信号而延迟第一脉冲信号，以产生具有较长活动的第二脉冲信号周期比第一脉冲信号。

8. 发明申请

US20110006823A1 SIGNAL DELAY CIRCUIT, CLOCK TRANSFER CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME 有权
标题翻译：信号延迟电路，时钟传输控制电路和具有该信号的半导体器件
公开(公告)号：US20110006823A1
公开(公告)日：2011-01-13
申请号：US12792530
申请日：2010-06-02
申请人： Hyoung-Jun NA , Kyung-Whan Kim
发明人： Hyoung-Jun NA , Kyung-Whan Kim
IPC分类号： H03K5/04
CPC分类号： H03K5/04
摘要： A signal delay circuit including a clock transfer control circuit configured to transmit or block a clock signal, and a pulse signal generation circuit configured to delay a first pulse signal in response to the transmitted clock signal to generate a second pulse signal which has a longer active period than the first pulse signal.
摘要翻译：一种信号延迟电路，包括被配置为发送或阻断时钟信号的时钟传送控制电路，以及脉冲信号生成电路，被配置为响应于发送的时钟信号而延迟第一脉冲信号，以产生具有较长活动的第二脉冲信号周期比第一脉冲信号。

9. 发明授权

US07813211B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07813211B2
公开(公告)日：2010-10-12
申请号：US11956822
申请日：2007-12-14
申请人： Kyung-Whan Kim , Seok-Cheol Yoon
发明人： Kyung-Whan Kim , Seok-Cheol Yoon
IPC分类号： G11C8/00 , G11C7/00
CPC分类号： G11C7/1078 , G11C7/1093 , G11C7/1096 , G11C11/4076 , G11C11/4096 , G11C2207/002
摘要： A semiconductor memory device having read and write operations includes a discrimination signal generating unit for generating a discrimination signal during the write operation; and a selective delay unit for receiving and selectively delaying a command-group signal in response to the discrimination signal.
摘要翻译：具有读和写操作的半导体存储器件包括：识别信号产生单元，用于在写操作期间产生鉴别信号; 以及选择延迟单元，用于响应于所述鉴别信号接收和选择性地延迟命令组信号。

10. 发明申请

US20100250994A1 DATA PATTERN DETECTING CIRCUIT AND OUTPUT DRIVER INCLUDING THE SAME 审中-公开
标题翻译：数据模式检测电路和输出驱动器，包括它们
公开(公告)号：US20100250994A1
公开(公告)日：2010-09-30
申请号：US12495332
申请日：2009-06-30
申请人： Chang-Kun Park , Yong-Ju Kim , Kyung-Whan Kim , Sung-Woo Han , Jae-Il Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang
发明人： Chang-Kun Park , Yong-Ju Kim , Kyung-Whan Kim , Sung-Woo Han , Jae-Il Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang
IPC分类号： G06F1/12
CPC分类号： G06F13/4077
摘要： Disclosed is an output driver capable of solving problems that occur when outputting the same data successively by using a data pattern detecting circuit. The data pattern detecting circuit includes a first data storage unit configured to receive data of a first line and store the received data until a next data is inputted through the first line, a second data storage unit configured to receive data of a second line and store the received data until a next data is inputted through the second line, and a detection signal output unit configured to activate a pattern detection signal when data stored in the first data storage unit and data stored in the second data storage unit have the same logic level.
摘要翻译：公开了一种能够解决通过使用数据模式检测电路连续输出相同数据时出现的问题的输出驱动器。数据模式检测电路包括：第一数据存储单元，被配置为接收第一行的数据并存储接收的数据，直到通过第一行输入下一个数据;第二数据存储单元，被配置为接收第二行的数据并存储所接收的数据直到通过第二行输入下一个数据;以及检测信号输出单元，被配置为当存储在第一数据存储单元中的数据和存储在第二数据存储单元中的数据具有相同的逻辑电平时激活模式检测信号。

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