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1. 发明授权

US07016255B2 Multi-port memory device 有权
标题翻译：多端口存储设备
公开(公告)号：US07016255B2
公开(公告)日：2006-03-21
申请号：US10876231
申请日：2004-06-23
申请人： Ihl-Ho Lee , Kyung-Whan Kim , Jae-Jin Lee
发明人： Ihl-Ho Lee , Kyung-Whan Kim , Jae-Jin Lee
IPC分类号： G11C7/00
CPC分类号： G11C7/1075 , G11C8/16 , G11C11/4097 , G11C29/846 , G11C2207/002
摘要： A multi-port memory device can avoid failure of the first high data during initial operation so that reliability and operation characteristic of the memory device can be improved. The multi-port memory device comprises a global data bus having a multiplicity of bus lines, a plurality of banks having a current sensing type transceiving structure for exchanging data with the global data bus, one or more ports having a current sensing type transceiving structure for exchanging data with the global data bus, a plurality of switches, each arranged between the corresponding bank and the bus lines of the global data bus for selectively connecting one of a redundant column and normal columns of the corresponding bank to the global data bus, and a controlling unit for restricting the turn-on period of the switches to the substantial operation period of the corresponding bank.
摘要翻译：多端口存储器件可以避免初始操作期间第一高数据的故障，从而可以提高存储器件的可靠性和操作特性。多端口存储器件包括具有多条总线线路的全局数据总线，多个存储体具有用于与全局数据总线交换数据的电流检测型收发结构，具有电流检测型收发结构的一个或多个端口与全局数据总线交换数据，多个开关，每个交换机布置在全局数据总线的对应组和总线之间，用于选择性地将对应组的冗余列和正常列之一连接到全局数据总线;以及控制单元，用于将开关的导通周期限制到相应银行的实质操作周期。

2. 发明申请

US20050259477A1 Multi-port memory device 有权
标题翻译：多端口存储设备
公开(公告)号：US20050259477A1
公开(公告)日：2005-11-24
申请号：US10877887
申请日：2004-06-25
申请人： Ihl-Ho Lee , Kyung-Whan Kim , Jae-Jin Lee
发明人： Ihl-Ho Lee , Kyung-Whan Kim , Jae-Jin Lee
IPC分类号： G11C11/409 , G06F12/00 , G11C7/10 , G11C7/20 , G11C11/401 , G11C11/4072 , G11C11/4096
CPC分类号： G11C7/1048 , G11C7/1075 , G11C7/20 , G11C11/4072 , G11C11/4096
摘要： There is provided a multi-port memory device, which is capable of preventing a first high data fail phenomenon at an initial operation in a current sensing type global data bus transmission/reception structure without causing a problem in a low data transmission. In the multi-port memory device having a data transmission/reception block (bank, port, global data bus connection block, etc.) which exchanges data with the global data bus in a current sensing type data transmission/reception structure, an initialization switch is used to discharge each global data bus line and an initialization signal generator controls the initialization switch. A first high data fail at the initial operation is caused by a high precharge level of the global data bus. According to the present invention, it is possible to lower a high precharge level without causing a problem in data transmission.
摘要翻译：提供了一种多端口存储器件，其能够在电流感测型全局数据总线发送/接收结构中的初始操作时防止第一高数据故障现象，而不会导致低数据传输中的问题。在具有在当前感测型数据发送/接收结构中与全局数据总线交换数据的数据发送/接收块（存储体，端口，全局数据总线连接块等）的多端口存储器件中，初始化开关用于放电每个全局数据总线，初始化信号发生器控制初始化开关。初始操作时的第一个高数据故障是由全局数据总线的高预充电电平引起的。根据本发明，可以在不引起数据传输的问题的情况下降低高预充电水平。

3. 发明申请

US20050249018A1 Multi-port memory device 有权
标题翻译：多端口存储设备
公开(公告)号：US20050249018A1
公开(公告)日：2005-11-10
申请号：US10876231
申请日：2004-06-23
申请人： Ihl-Ho Lee , Kyung-Whan Kim , Jae-Jin Lee
发明人： Ihl-Ho Lee , Kyung-Whan Kim , Jae-Jin Lee
IPC分类号： G11C11/409 , G11C7/10 , G11C8/00 , G11C8/16 , G11C11/401 , G11C11/4097 , G11C29/00
CPC分类号： G11C7/1075 , G11C8/16 , G11C11/4097 , G11C29/846 , G11C2207/002
摘要： A multi-port memory device can avoid failure of the first high data during initial operation so that reliability and operation characteristic of the memory device can be improved. The multi-port memory device comprises a global data bus having a multiplicity of bus lines, a plurality of banks having a current sensing type transceiving structure for exchanging data with the global data bus, one or more ports having a current sensing type transceiving structure for exchanging data with the global data bus, a plurality of switches, each arranged between the corresponding bank and the bus lines of the global data bus for selectively connecting one of a redundant column and normal columns of the corresponding bank to the global data bus, and a controlling unit for restricting the turn-on period of the switches to the substantial operation period of the corresponding bank.
摘要翻译：多端口存储器件可以避免初始操作期间第一高数据的故障，从而可以提高存储器件的可靠性和操作特性。多端口存储器件包括具有多条总线线路的全局数据总线，多个存储体具有用于与全局数据总线交换数据的电流检测型收发结构，具有电流检测型收发结构的一个或多个端口与全局数据总线交换数据，多个开关，每个交换机布置在全局数据总线的对应组和总线之间，用于选择性地将对应组的冗余列和正常列之一连接到全局数据总线;以及控制单元，用于将开关的导通周期限制到相应银行的实质操作周期。

4. 发明授权

US07305516B2 Multi-port memory device with precharge control 有权
标题翻译：具有预充电控制功能的多端口存储器件
公开(公告)号：US07305516B2
公开(公告)日：2007-12-04
申请号：US10877887
申请日：2004-06-25
申请人： Ihl-Ho Lee , Kyung-Whan Kim , Jae-Jin Lee
发明人： Ihl-Ho Lee , Kyung-Whan Kim , Jae-Jin Lee
IPC分类号： G06F12/00
CPC分类号： G11C7/1048 , G11C7/1075 , G11C7/20 , G11C11/4072 , G11C11/4096
摘要： There is provided a multi-port memory device, which is capable of preventing a first high data fail phenomenon at an initial operation in a current sensing type global data bus transmission/reception structure without causing a problem in a low data transmission. In the multi-port memory device having a data transmission/reception block (bank, port, global data bus connection block, etc.) which exchanges data with the global data bus in a current sensing type data transmission/reception structure, an initialization switch is used to discharge each global data bus line and an initialization signal generator controls the initialization switch. A first high data fail at the initial operation is caused by a high precharge level of the global data bus. According to the present invention, it is possible to lower a high precharge level without causing a problem in data transmission.
摘要翻译：提供了一种多端口存储器件，其能够在电流感测型全局数据总线发送/接收结构中的初始操作时防止第一高数据故障现象，而不会导致低数据传输中的问题。在具有在当前感测型数据发送/接收结构中与全局数据总线交换数据的数据发送/接收块（存储体，端口，全局数据总线连接块等）的多端口存储器件中，初始化开关用于放电每个全局数据总线，初始化信号发生器控制初始化开关。初始操作时的第一个高数据故障是由全局数据总线的高预充电电平引起的。根据本发明，可以在不引起数据传输的问题的情况下降低高预充电水平。

5. 发明授权

US07602656B2 Power supply control circuit and controlling method thereof 失效
标题翻译：电源控制电路及其控制方法
公开(公告)号：US07602656B2
公开(公告)日：2009-10-13
申请号：US12098229
申请日：2008-04-04
申请人： Ihl-Ho Lee
发明人： Ihl-Ho Lee
IPC分类号： G11C5/14 , G11C7/22 , G11C7/10
CPC分类号： G11C7/1066 , G11C5/147 , G11C7/1048
摘要： A power supply control circuit and a control method secure an accurate operation of a GIO in a burst data transmission having a high compression rate. The power supply control circuit of a semiconductor memory device includes: a counter which is reset in response to a read command signal or a write command signal to count an input clock and then, to output a counting completion signal; and a power supply enable signal generator enabled in response to the read command signal or the write command signal and disabled in response to the counting completion signal, for generating a power supply enable signal.
摘要翻译：电源控制电路和控制方法确保了具有高压缩率的突发数据传输中的GIO的精确操作。半导体存储器件的电源控制电路包括：响应于读命令信号复位的计数器或对输入时钟进行计数的写命令信号，然后输出计数完成信号; 以及电源使能信号发生器，其响应于所述读取命令信号或所述写入命令信号而被使能，并且响应于所述计数完成信号被禁用，以产生电源使能信号。

6. 发明申请

US20080198672A1 Power Supply Control Circuit and Controlling Method Thereof 失效
标题翻译：电源控制电路及其控制方法
公开(公告)号：US20080198672A1
公开(公告)日：2008-08-21
申请号：US12098229
申请日：2008-04-04
申请人： Ihl-Ho Lee
发明人： Ihl-Ho Lee
IPC分类号： G11C7/00 , G11C5/14 , G11C8/00
CPC分类号： G11C7/1066 , G11C5/147 , G11C7/1048
摘要： The present invention provides a power supply control circuit and a control method thereof, capable of securing an accurate operation of a GIO in a burst data transmission having a high compression rate. The power supply control circuit of a semiconductor memory device includes: a counter which is reset in response to a read command signal or a write command signal to count an input clock and then, to output a counting completion signal; and a power supply enable signal generator enabled in response to the read command signal or the write command signal and disabled in response to the counting completion signal, for generating a power supply enable signal.
摘要翻译：本发明提供一种电源控制电路及其控制方法，其能够确保GIO在具有高压缩率的突发数据传输中的精确操作。半导体存储器件的电源控制电路包括：响应于读命令信号复位的计数器或对输入时钟进行计数的写命令信号，然后输出计数完成信号; 以及电源使能信号发生器，其响应于所述读取命令信号或所述写入命令信号而被使能，并且响应于所述计数完成信号被禁用，以产生电源使能信号。

7. 发明授权

US06987699B2 Clock driver in semiconductor memory device 有权
标题翻译：半导体存储器件中的时钟驱动器
公开(公告)号：US06987699B2
公开(公告)日：2006-01-17
申请号：US10331351
申请日：2002-12-31
申请人： Ihl-Ho Lee
发明人： Ihl-Ho Lee
IPC分类号： G11C7/00
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/222
摘要： A clock driver in a semiconductor memory device does not output a rising edge clock signal and a falling edge clock signal outputted from a DLL circuit when there are no data transmitted to a data output pin in a read operation. A clock driver which can reduce current consumption by suppressing output of a rising edge clock signal and a falling edge clock signal in a stand-by mode in a semiconductor memory device. The clock driver for use in a semiconductor memory device according to the present invention does not output a rising edge clock signal and a falling edge clock signal outputted from a DLL circuit when there is no data transmitted to a data output pin in a read operation.
摘要翻译：半导体存储器件中的时钟驱动器在读操作中没有数据发送到数据输出引脚时，不输出从DLL电路输出的上升沿时钟信号和下降沿时钟信号。一种时钟驱动器，其通过在半导体存储器件中以待机模式抑制上升沿时钟信号和下降沿时钟信号的输出而降低电流消耗。当在读取操作中没有数据发送到数据输出引脚时，根据本发明的用于半导体存储器件的时钟驱动器不输出从DLL电路输出的上升沿时钟信号和下降沿时钟信号。

8. 发明授权

US06480434B1 Memory device with precharge reinforcement circuit 有权
标题翻译：带预充电电路的存储器
公开(公告)号：US06480434B1
公开(公告)日：2002-11-12
申请号：US10029937
申请日：2001-12-31
申请人： Ihl-Ho Lee
发明人： Ihl-Ho Lee
IPC分类号： G11C700
CPC分类号： G11C7/12
摘要： A memory device includes: a plurality of cell array blocks provided with a plurality of memory cells coupled to a word line and a bit line pair; a bit line control block including a first control block and a second control block, wherein the first control block is separately coupled to a first bit line pair coupled to a first cell array block among the cell array blocks, and the second control block is shared with a second bit line pair commonly coupled to the first cell array block and a second cell array block adjacent to the first cell array block; and a precharge reinforcement unit, coupled to a predetermined portion of the first control block, for reducing a precharge speed difference between the first bit line pair and the second bit line pair.
摘要翻译：存储器件包括：多个单元阵列块，其设置有耦合到字线和位线对的多个存储单元; 包括第一控制块和第二控制块的位线控制块，其中所述第一控制块分别耦合到耦合到所述单元阵列块中的第一单元阵列块的第一位线对，并且所述第二控制块被共享通常耦合到第一单元阵列块的第二位线对和与第一单元阵列块相邻的第二单元阵列块; 以及预充电加强单元，耦合到第一控制块的预定部分，用于减小第一位线对和第二位线对之间的预充电速度差。

9. 发明授权

US07831845B2 Power-up circuit and semiconductor memory apparatus with the same 失效
标题翻译：上电电路和半导体存储器具相同
公开(公告)号：US07831845B2
公开(公告)日：2010-11-09
申请号：US11594855
申请日：2006-11-09
申请人： Ihl-Ho Lee
发明人： Ihl-Ho Lee
IPC分类号： G06F1/00 , G06F1/26 , G06F5/14
CPC分类号： G11C7/20 , G11C5/143 , G11C11/4072 , G11C11/4074 , G11C2207/2227
摘要： A power-up circuit includes a power-up signal generating section connected to an external source terminal, configured to generate a power-up signal when the external source reaches a predetermined target level, and to selectively interrupt a path from the external source terminal in response to a selection signal. A pulse generating section generates a pulse with a predetermined pulse width to control an initializing operation with reference to an activation time of the power-up signal. A power-up controlling section provides the power-up signal generating section with the selection signal, variable by the pulse, when the power-up signal is active.
摘要翻译：上电电路包括连接到外部源极端子的上电信号发生部分，被配置为当外部源达到预定目标电平时产生上电信号，并且选择性地中断来自外部源极端子的路径响应选择信号。脉冲发生部分产生具有预定脉冲宽度的脉冲，以参照上电信号的激活时间来控制初始化操作。上电控制部分在上电信号有效时向上电信号发生部分提供可由脉冲变化的选择信号。

10. 发明授权

US07352644B2 Semiconductor memory with reset function 失效
标题翻译：具有复位功能的半导体存储器
公开(公告)号：US07352644B2
公开(公告)日：2008-04-01
申请号：US11531370
申请日：2006-09-13
申请人： Ihl-Ho Lee
发明人： Ihl-Ho Lee
IPC分类号： G11C7/20 , G11C7/22
CPC分类号： G11C7/20 , G11C7/1045 , G11C7/1078 , G11C7/109 , G11C11/4072 , G11C11/4093
摘要： A synchronous dynamic random access memory (SDRAM) integrated circuit (IC) configured to receive an external Reset signal for resetting the IC includes an input buffer configured to generate a buffered reset signal RST from the external Reset signal. The SDRAM IC further includes a reset circuit is configured to generate an internal reset signal Reset_En from (a) the RST signal, (b) a clock enable signal CKE which indicates a time when the SDRAM is ready to receive an external command, and (c) a mode register programming signal MRSP which indicates a time when a mode register is to be loaded with data.
摘要翻译：被配置为接收用于复位IC的外部复位信号的同步动态随机存取存储器（SDRAM）集成电路（IC）包括被配置为从外部复位信号产生缓冲复位信号RST的输入缓冲器。 SDRAM IC还包括复位电路，其被配置为从（a）RST信号产生内部复位信号Reset_En，（b）指示SDRAM准备好接收外部命令的时间的时钟使能信号CKE，以及（ c）指示模式寄存器要被加载数据的时间的模式寄存器编程信号MRS 。

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