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1. 发明授权

US09396988B2 Methods for fabricating semiconductor devices using liner layers to avoid damage to underlying patterns 有权
标题翻译：使用衬里层制造半导体器件以避免损坏底层图案的方法
公开(公告)号：US09396988B2
公开(公告)日：2016-07-19
申请号：US14703556
申请日：2015-05-04
申请人： Kyoung-Woo Lee , Woo-Jin Lee , Jong-Sam Kim , Woo-Kyung You , Young-Sang Lee , Min Huh
发明人： Kyoung-Woo Lee , Woo-Jin Lee , Jong-Sam Kim , Woo-Kyung You , Young-Sang Lee , Min Huh
IPC分类号： H01L21/02 , H01L21/311 , H01L21/70 , H01L21/768
CPC分类号： H01L21/76802 , H01L21/31144 , H01L21/76804 , H01L21/76811 , H01L21/76813 , H01L21/76814 , H01L21/76843 , H01L2221/1063
摘要： A method for fabricating a semiconductor device includes sequentially forming an interlayer insulating layer and a hard mask pattern including a first opening on a substrate including a lower pattern, forming a trench exposing the lower pattern in the interlayer insulating layer using the hard mask pattern, forming a liner layer including a first part formed along sidewalls and a bottom surface of the trench and a second part formed along a top surface of the hard mask pattern, forming a sacrificial pattern exposing the second part of the liner layer in the trench, removing the second part of the liner layer and the hard mask pattern using the sacrificial pattern, and after the removing of the hard mask pattern, removing the sacrificial pattern to expose the first part of the liner layer.
摘要翻译：一种制造半导体器件的方法包括在包括下图案的衬底上顺序地形成层间绝缘层和包括第一开口的硬掩模图案，使用硬掩模图案形成在层间绝缘层中暴露下图案的沟槽，形成包括沿着沟槽的侧壁和底表面形成的第一部分和沿着硬掩模图案的顶表面形成的第二部分的衬垫层，形成暴露沟槽中的衬垫层的第二部分的牺牲图案，衬垫层的第二部分和使用牺牲图案的硬掩模图案，并且在去除硬掩模图案之后，去除牺牲图案以露出衬垫层的第一部分。

2. 发明申请

US20160079115A1 Methods for Fabricating Semiconductor Devices Using Liner Layers to Avoid Damage to Underlying Patterns 有权
标题翻译：使用衬垫层制造半导体器件以避免损害底层图案的方法
公开(公告)号：US20160079115A1
公开(公告)日：2016-03-17
申请号：US14703556
申请日：2015-05-04
申请人： Kyoung-Woo Lee , Woo-Jin Lee , Jong-Sam Kim , Woo-Kyung You , Young-Sang Lee , Min Huh
发明人： Kyoung-Woo Lee , Woo-Jin Lee , Jong-Sam Kim , Woo-Kyung You , Young-Sang Lee , Min Huh
IPC分类号： H01L21/768
CPC分类号： H01L21/76802 , H01L21/31144 , H01L21/76804 , H01L21/76811 , H01L21/76813 , H01L21/76814 , H01L21/76843 , H01L2221/1063
摘要： A method for fabricating a semiconductor device includes sequentially forming an interlayer insulating layer and a hard mask pattern including a first opening on a substrate including a lower pattern, forming a trench exposing the lower pattern in the interlayer insulating layer using the hard mask pattern, forming a liner layer including a first part formed along sidewalls and a bottom surface of the trench and a second part formed along a top surface of the hard mask pattern, forming a sacrificial pattern exposing the second part of the liner layer in the trench, removing the second part of the liner layer and the hard mask pattern using the sacrificial pattern, and after the removing of the hard mask pattern, removing the sacrificial pattern to expose the first part of the liner layer.
摘要翻译：一种制造半导体器件的方法包括在包括下图案的衬底上顺序地形成层间绝缘层和包括第一开口的硬掩模图案，使用硬掩模图案形成在层间绝缘层中暴露下图案的沟槽，形成包括沿着沟槽的侧壁和底表面形成的第一部分和沿着硬掩模图案的顶表面形成的第二部分的衬垫层，形成暴露沟槽中的衬垫层的第二部分的牺牲图案，衬垫层的第二部分和使用牺牲图案的硬掩模图案，并且在去除硬掩模图案之后，去除牺牲图案以露出衬垫层的第一部分。

3. 发明授权

US10229876B2 Wiring structures and semiconductor devices 有权
公开(公告)号：US10229876B2
公开(公告)日：2019-03-12
申请号：US15073640
申请日：2016-03-17
申请人： Jun-Jung Kim , Young-Bae Kim , Jong-Sam Kim , Jin-Hyeung Park , Jeong-Hoon Ahn , Hyeok-Sang Oh , Kyoung-Woo Lee , Hyo-Seon Lee , Suk-Hee Jang
发明人： Jun-Jung Kim , Young-Bae Kim , Jong-Sam Kim , Jin-Hyeung Park , Jeong-Hoon Ahn , Hyeok-Sang Oh , Kyoung-Woo Lee , Hyo-Seon Lee , Suk-Hee Jang
IPC分类号： H01L23/535 , H01L23/528 , H01L23/522 , H01L27/088 , H01L23/532 , H01L21/768 , H01L21/8234 , H01L23/485
摘要： A wiring structure includes a substrate, a lower insulation layer on the substrate, a lower wiring in the lower insulation layer, a first etch-stop layer covering the lower wiring and including a metallic dielectric material, a second etch-stop layer on the first etch-stop layer and the lower insulation layer, an insulating interlayer on the second etch-stop layer, and a conductive pattern extending through the insulating interlayer, the second etch-stop layer and the first etch-stop layer and electrically connected to the lower wiring.

4. 发明授权

US08384131B2 Semiconductor device and methods of forming the same 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US08384131B2
公开(公告)日：2013-02-26
申请号：US12187271
申请日：2008-08-06
申请人： Kyoung-Woo Lee , Andrew Tae Kim , Hong-Jae Shin
发明人： Kyoung-Woo Lee , Andrew Tae Kim , Hong-Jae Shin
IPC分类号： H01L27/10
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device includes a fuse structure disposed on a substrate. An interlayer dielectric disposed on the fuse structure. A first contact plug, a second contact plug, and a third contact plug penetrate the interlayer dielectric and wherein each of the first contact plug, the second contact plug and the third contact plug are connected to the fuse structure. A first conductive pattern and a second conductive pattern are disposed on the interlayer dielectric. The first conductive pattern and the second conductive pattern are electrically connected to the first contact plug and second contact plug, respectively.
摘要翻译：半导体器件包括设置在衬底上的熔丝结构。设置在熔丝结构上的层间电介质。第一接触插塞，第二接触插塞和第三接触插塞穿透层间电介质，并且其中第一接触插塞，第二接触插塞和第三接触插塞中的每一个连接到熔丝结构。第一导电图案和第二导电图案设置在层间绝缘体上。第一导电图案和第二导电图案分别电连接到第一接触插塞和第二接触插塞。

5. 发明授权

US07568024B2 Method for deciding network manager in home network 有权
标题翻译：在家庭网络中决定网络管理员的方法
公开(公告)号：US07568024B2
公开(公告)日：2009-07-28
申请号：US10337316
申请日：2003-01-07
申请人： Kyoung-Woo Lee , Seung-Cheon Kim , Sang-Wook Lim
发明人： Kyoung-Woo Lee , Seung-Cheon Kim , Sang-Wook Lim
IPC分类号： G06F15/173
CPC分类号： H04L41/00 , H04L12/2803
摘要： A method for deciding a network manager (NM) in a home network, including the steps of comparing a priority of a current NM and a priority of a new NM when the new NM is plugged-in a home network which is controlled by the current NM and deciding a NM having a higher priority as the NM of the home network between the current NM and the new NM, can smoothly control and manage the home network by deciding a NM having a higher priority as the NM for centralized-controlling the home network.
摘要翻译：一种用于在家庭网络中确定网络管理器（NM）的方法，包括以下步骤：当新的NM被插入由当前所控制的家庭网络时，将当前NM的优先级与新NM的优先级进行比较 NM并且将具有较高优先级的NM作为当前NM和新NM之间的归属网络的NM可以通过将具有较高优先级的NM确定为用于集中控制家庭的NM来平滑地控制和管理归属网络网络。

6. 发明申请

US20070184649A1 Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics 有权
标题翻译：使用具有不同孔隙率特性的多个平坦化层在半导体衬底上形成双镶嵌互连结构的方法
公开(公告)号：US20070184649A1
公开(公告)日：2007-08-09
申请号：US11348428
申请日：2006-02-06
申请人： Kyoung-Woo Lee , Seung-Man Choi , Ja-Hum Ku , Ki-Chul Park , Sun Kim
发明人： Kyoung-Woo Lee , Seung-Man Choi , Ja-Hum Ku , Ki-Chul Park , Sun Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/31144
摘要： Methods of forming integrated circuit devices include patterning an electrically insulating layer to support dual-damascene interconnect structures therein. The steps of patterning the electrically insulating layer include using multiple planarization layers having different porosity characteristics. Forming an interconnect structure within an integrated circuit device may include forming an electrically insulating layer on a substrate and forming at least one via hole extending at least partially through the electrically insulating layer. The at least one via hole is filled with a first electrically insulating material having a first porosity. The filled at least one via hole is then covered with a second electrically insulating material layer having a second porosity lower than the first porosity. The second electrically insulating material layer is selectively etched back to expose a first portion of the first electrically insulating material in the at least one via hole. The electrically insulating layer is selectively etched to define a trench therein that exposes a second portion of the first electrically insulating material in the at least one via hole. The first electrically insulating material, which has a relatively high degree of porosity, is then removed from the at least one via hole. This removal step may be performed using a relatively mild ashing process because of the high porosity of the first electrically insulating material.
摘要翻译：形成集成电路器件的方法包括图案化电绝缘层以支持其中的双镶嵌互连结构。图案化电绝缘层的步骤包括使用具有不同孔隙特性的多个平坦化层。在集成电路器件内形成互连结构可以包括在衬底上形成电绝缘层，并形成至少部分穿过电绝缘层延伸的至少一个通孔。至少一个通孔填充有具有第一孔隙率的第一电绝缘材料。填充的至少一个通孔然后被具有低于第一孔隙率的第二孔隙率的第二电绝缘材料层覆盖。选择性地回蚀第二电绝缘材料层以暴露至少一个通孔中的第一电绝缘材料的第一部分。电绝缘层被选择性蚀刻以在其中限定其中的沟槽，其暴露出至少一个通孔中的第一电绝缘材料的第二部分。然后从该至少一个通孔去除具有较高孔隙率的第一电绝缘材料。由于第一电绝缘材料的高孔隙率，该去除步骤可以使用相对温和的灰化过程进行。

7. 发明申请

US20050124149A1 Method of forming dual damascene metal interconnection employing sacrificial metal oxide layer 有权
标题翻译：使用牺牲金属氧化物层形成双镶嵌金属互连的方法
公开(公告)号：US20050124149A1
公开(公告)日：2005-06-09
申请号：US10939930
申请日：2004-09-13
申请人： Jae-Hak Kim , Young-Joon Moon , Kyoung-Woo Lee , Jeong-Wook Hwang
发明人： Jae-Hak Kim , Young-Joon Moon , Kyoung-Woo Lee , Jeong-Wook Hwang
IPC分类号： H01L21/28 , H01L21/311 , H01L21/768 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/76808 , H01L21/31144
摘要： There is provided a method of forming a dual damascene metal interconnection by employing a sacrificial metal oxide layer. The method includes preparing a semiconductor substrate. An interlayer insulating layer is formed on the semiconductor substrate, and a preliminary via hole is formed by patterning the interlayer insulating layer. A sacrificial via protecting layer is formed on the semiconductor substrate having the preliminary via hole to fill the preliminary via hole, and cover an upper surface of the interlayer insulating layer. A sacrificial metal oxide layer is formed on the sacrificial via protecting layer, the sacrificial metal oxide layer is patterned to form a sacrificial metal oxide pattern having an opening crossing over the preliminary via hole, and exposing the sacrificial via protecting layer. The sacrificial via protecting layer and the interlayer insulating layer are etched using the sacrificial metal oxide pattern as an etch mask to form a trench located inside the interlayer insulating layer.
摘要翻译：提供了通过使用牺牲金属氧化物层形成双镶嵌金属互连的方法。该方法包括制备半导体衬底。在半导体基板上形成层间绝缘层，通过图案化层间绝缘层形成预备通孔。在具有初步通孔的半导体衬底上形成牺牲通孔保护层以填充预通孔，并覆盖层间绝缘层的上表面。在牺牲通路保护层上形成牺牲金属氧化物层，对牺牲金属氧化物层进行图案化以形成具有穿过预通孔的开口的牺牲金属氧化物图案，并且将牺牲通过保护层曝光。使用牺牲金属氧化物图案作为蚀刻掩模蚀刻牺牲通过保护层和层间绝缘层，以形成位于层间绝缘层内部的沟槽。

8. 发明申请

US20050088551A1 Structure of a CMOS image sensor and method for fabricating the same 有权
公开(公告)号：US20050088551A1
公开(公告)日：2005-04-28
申请号：US10973291
申请日：2004-10-27
申请人： Soo-Geun Lee , Ki-Chul Park , Kyoung-Woo Lee
发明人： Soo-Geun Lee , Ki-Chul Park , Kyoung-Woo Lee
IPC分类号： G01R31/28 , H01L23/532 , H01L27/146 , H01L31/0224 , H04N17/00 , H04N5/335
CPC分类号： H01L23/53238 , G01R31/2829 , H01L21/76805 , H01L27/14603 , H01L27/14623 , H01L27/14627 , H01L27/14636 , H01L27/14687 , H01L31/022408 , H01L2924/0002 , H04N17/002 , H01L2924/00
摘要： An image sensor device and method for forming the same include a photodiode formed in a substrate, at least one electrical interconnection line electrically associated with the photodiode, a light passageway having a light inlet, the light passageway being positioned in alignment with the photodiode, a color filter positioned over the light inlet of the light passageway and a lens positioned over the color filter in alignment with the light passageway wherein the at least one electrical interconnection line includes a copper interconnection formation having a plurality of interlayer dielectric layers in a stacked configuration with a diffusion barrier layer between adjacent interlayer dielectric layers, and a barrier metal layer between the copper interconnection formation and the plurality of interlayer dielectric layers and intervening diffusion barrier layers. An image sensor device may employ copper interconnections if a barrier metal layer is removed from above a photodiode.

9. 发明授权

US6158017A Method for storing parity and rebuilding data contents of failed disks in an external storage subsystem and apparatus thereof 失效
标题翻译：在外部存储子系统中存储奇偶校验和重建故障盘的数据内容的方法及其装置
公开(公告)号：US6158017A
公开(公告)日：2000-12-05
申请号：US39679
申请日：1998-03-16
申请人： Tack-Don Han , Shin-Dug Kim , Sung-Bong Yang , Kyoung-Woo Lee , Suk Chang
发明人： Tack-Don Han , Shin-Dug Kim , Sung-Bong Yang , Kyoung-Woo Lee , Suk Chang
IPC分类号： G06F12/16 , G06F3/06 , G06F11/10 , H03M13/00 , H03M13/09 , H03M13/29
CPC分类号： G06F11/1076 , H03M13/00 , H03M13/09 , H03M13/29 , H03M13/2921 , H03M13/6561
摘要： A method for storing parity and rebuilding the data contents of two failed disks in an external storage subsystem comprises the steps of: proving a disk array defined as a matrix of (N-1).sup.* N including N disks each logically divided into N-1 data blocks where N is a prime number, the data blocks of a row being defined as a horizontal parity group, the data blocks existing in a rightwardly and upwardly continuous diagonal line being defined as a diagonal parity group; defining the data blocks existing in the diagonal line leftwardly and downwardly from the first data block of the (N-1) disk to the last data block of the first disk as horizontal parity blocks; defining the data blocks existing in the (N-1) row of the matrix as diagonal parity blocks; exclusive OR'ing (XORing) the contents of each of the horizontal and diagonal parity groups to obtain the parity value stored into the parity block of the corresponding horizontal or diagonal parity group; and analyzing a diagonal parity group including an error data block of the two failed disks to restore the error data block and then, the horizontal parity group including the restored error data block to restore another error data block, wherein the last analyzing step is repeated to completely rebuild the data contents of the two failed disks.
摘要翻译：一种在外部存储子系统中存储奇偶校验和重建两个故障磁盘的数据内容的方法，包括以下步骤：证明定义为包括N个磁盘的（N-1）* N的矩阵的磁盘阵列，每个N个磁盘每个逻辑上划分为N-1个数据块，其中N是素数，一行的数据块被定义为水平奇偶校验组，存在于向右和向上连续的对角线中的数据块被定义为对角奇偶校验组; 将存在于对角线中的数据块从（N-1）盘的第一数据块向左和向下定位为第一盘的最后数据块作为水平校验块; 将存在于矩阵的（N-1）行中的数据块定义为对角奇偶校验块; 对每个水平和对角奇偶校验组的内容进行异或运算（异或），以获得存储在相应的水平或对角奇偶校验组的奇偶校验块中的奇偶校验值; 并且分析包括两个故障磁盘的错误数据块的对角奇偶校验组以恢复错误数据块，然后，包括恢复的错误数据块的水平奇偶校验组以恢复另一个错误数据块，其中重复最后一个分析步骤完全重建两个故障磁盘的数据内容。

10. 发明授权

US07989335B2 Methods of forming insulation layer patterns and methods of manufacturing semiconductor devices including insulation layer patterns 有权
标题翻译：形成绝缘层图案的方法和制造包括绝缘层图案的半导体器件的方法
公开(公告)号：US07989335B2
公开(公告)日：2011-08-02
申请号：US12661885
申请日：2010-03-25
申请人： Kyoung-Woo Lee , Hong-Jae Shin
发明人： Kyoung-Woo Lee , Hong-Jae Shin
IPC分类号： H01L21/44
CPC分类号： H01L27/10852 , H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L21/76816 , H01L28/91
摘要： In a method of forming an insulation layer pattern, an insulation layer is formed on a substrate. An organic layer and a hard mask layer are successively formed on the insulation layer. A preliminary hard mask pattern having first openings is formed by patterning the hard mask layer. A hard mask pattern having the first openings and second openings is formed by patterning the preliminary hard mask pattern. Width control spacers are formed on sidewalls of the first and the second openings. An etching mask pattern is formed by etching the organic layer using the hard mask pattern as an etching mask. The insulation layer pattern having third openings is formed by etching the insulation layer using the etching mask pattern as an etching mask.
摘要翻译：在形成绝缘层图案的方法中，在基板上形成绝缘层。在绝缘层上依次形成有机层和硬掩模层。通过图案化硬掩模层形成具有第一开口的初步硬掩模图案。具有第一开口和第二开口的硬掩模图案通过图案化初步硬掩模图案而形成。宽度控制间隔件形成在第一和第二开口的侧壁上。通过使用硬掩模图案作为蚀刻掩模蚀刻有机层来形成蚀刻掩模图案。通过使用蚀刻掩模图案作为蚀刻掩模蚀刻绝缘层来形成具有第三开口的绝缘层图案。

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