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1. 发明申请

US20050088551A1 Structure of a CMOS image sensor and method for fabricating the same 有权
公开(公告)号：US20050088551A1
公开(公告)日：2005-04-28
申请号：US10973291
申请日：2004-10-27
申请人： Soo-Geun Lee , Ki-Chul Park , Kyoung-Woo Lee
发明人： Soo-Geun Lee , Ki-Chul Park , Kyoung-Woo Lee
IPC分类号： G01R31/28 , H01L23/532 , H01L27/146 , H01L31/0224 , H04N17/00 , H04N5/335
CPC分类号： H01L23/53238 , G01R31/2829 , H01L21/76805 , H01L27/14603 , H01L27/14623 , H01L27/14627 , H01L27/14636 , H01L27/14687 , H01L31/022408 , H01L2924/0002 , H04N17/002 , H01L2924/00
摘要： An image sensor device and method for forming the same include a photodiode formed in a substrate, at least one electrical interconnection line electrically associated with the photodiode, a light passageway having a light inlet, the light passageway being positioned in alignment with the photodiode, a color filter positioned over the light inlet of the light passageway and a lens positioned over the color filter in alignment with the light passageway wherein the at least one electrical interconnection line includes a copper interconnection formation having a plurality of interlayer dielectric layers in a stacked configuration with a diffusion barrier layer between adjacent interlayer dielectric layers, and a barrier metal layer between the copper interconnection formation and the plurality of interlayer dielectric layers and intervening diffusion barrier layers. An image sensor device may employ copper interconnections if a barrier metal layer is removed from above a photodiode.

2. 发明授权

US07400003B2 Structure of a CMOS image sensor and method for fabricating the same 有权
标题翻译： CMOS图像传感器的结构及其制造方法
公开(公告)号：US07400003B2
公开(公告)日：2008-07-15
申请号：US10998803
申请日：2004-11-30
申请人： Soo-Geun Lee , Ki-Chul Park , Kyoung-Woo Lee
发明人： Soo-Geun Lee , Ki-Chul Park , Kyoung-Woo Lee
IPC分类号： H01L31/062
CPC分类号： H01L23/53238 , G01R31/2829 , H01L21/76805 , H01L27/14603 , H01L27/14623 , H01L27/14627 , H01L27/14636 , H01L27/14687 , H01L31/022408 , H01L2924/0002 , H04N17/002 , H01L2924/00
摘要： An image sensor device and method for forming the same include a photodiode formed in a substrate, at least one electrical interconnection line electrically associated with the photodiode, a light passageway having a light inlet, the light passageway being positioned in alignment with the photodiode, a color filter positioned over the light inlet of the light passageway and a lens positioned over the color filter in alignment with the light passageway wherein the at least one electrical interconnection line includes a copper interconnection formation having a plurality of interlayer dielectric layers in a stacked configuration with a diffusion barrier layer between adjacent interlayer dielectric layers, and a barrier metal layer between the copper interconnection formation and the plurality of interlayer dielectric layers and intervening diffusion barrier layers. An image sensor device may employ copper interconnections if a barrier metal layer is removed from above a photodiode.
摘要翻译：图像传感器装置及其形成方法包括形成在基板中的光电二极管，与光电二极管电连接的至少一个电互连线，具有光入口的光通路，光通路与光电二极管对准，位于光通道的光入口之上的滤色器和位于滤光器上的透镜与光通路对准，其中至少一个电互连线包括铜互连结构，铜互连结构具有层叠形式的多个层间电介质层，相邻的层间电介质层之间的扩散阻挡层和铜互连结构与多个层间电介质层之间的阻挡金属层以及介于其间的扩散阻挡层。如果从光电二极管上方去除阻挡金属层，则图像传感器装置可以采用铜互连。

3. 发明授权

US06861686B2 Structure of a CMOS image sensor and method for fabricating the same 有权
公开(公告)号：US06861686B2
公开(公告)日：2005-03-01
申请号：US10633709
申请日：2003-08-05
申请人： Soo-Geun Lee , Ki-Chul Park , Kyoung-Woo Lee
发明人： Soo-Geun Lee , Ki-Chul Park , Kyoung-Woo Lee
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L23/532 , H01L27/14 , H01L27/146 , H01L31/0224 , H04N5/335 , H04N5/369 , H04N5/374 , H01L31/062 , H01L31/113
CPC分类号： H01L31/022408 , H01L21/76801 , H01L21/76805 , H01L21/76807 , H01L21/76843 , H01L21/76844 , H01L21/76865 , H01L23/53238 , H01L27/14623 , H01L27/14625 , H01L27/14627 , H01L27/14629 , H01L27/14632 , H01L27/14636 , H01L27/14685 , H01L2924/0002 , H01L2924/00
摘要： An image sensor device and method for forming the same include a photodiode formed in a substrate, at least one electrical interconnection line electrically associated with the photodiode, a light passageway having a light inlet, the light passageway being positioned in alignment with the photodiode, a color filter positioned over the light inlet of the light passageway and a lens positioned over the color filter in alignment with the light passageway wherein the at least one electrical interconnection line includes a copper interconnection formation having a plurality of interlayer dielectric layers in a stacked configuration with a diffusion barrier layer between adjacent interlayer dielectric layers, and a barrier metal layer between the copper interconnection formation and the plurality of interlayer dielectric layers and intervening diffusion barrier layers. An image sensor device may employ copper interconnections if a barrier metal layer is removed from above a photodiode.

4. 发明授权

US07462507B2 Structure of a CMOS image sensor and method for fabricating the same 有权
公开(公告)号：US07462507B2
公开(公告)日：2008-12-09
申请号：US10973291
申请日：2004-10-27
申请人： Soo-Geun Lee , Ki-Chul Park , Kyoung-Woo Lee
发明人： Soo-Geun Lee , Ki-Chul Park , Kyoung-Woo Lee
IPC分类号： H01L21/00
CPC分类号： H01L23/53238 , G01R31/2829 , H01L21/76805 , H01L27/14603 , H01L27/14623 , H01L27/14627 , H01L27/14636 , H01L27/14687 , H01L31/022408 , H01L2924/0002 , H04N17/002 , H01L2924/00
摘要： An image sensor device and method for forming the same include a photodiode formed in a substrate, at least one electrical interconnection line electrically associated with the photodiode, a light passageway having a light inlet, the light passageway being positioned in alignment with the photodiode, a color filter positioned over the light inlet of the light passageway and a lens positioned over the color filter in alignment with the light passageway wherein the at least one electrical interconnection line includes a copper interconnection formation having a plurality of interlayer dielectric layers in a stacked configuration with a diffusion barrier layer between adjacent interlayer dielectric layers, and a barrier metal layer between the copper interconnection formation and the plurality of interlayer dielectric layers and intervening diffusion barrier layers. An image sensor device may employ copper interconnections if a barrier metal layer is removed from above a photodiode.

5. 发明申请

US20070184649A1 Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics 有权
标题翻译：使用具有不同孔隙率特性的多个平坦化层在半导体衬底上形成双镶嵌互连结构的方法
公开(公告)号：US20070184649A1
公开(公告)日：2007-08-09
申请号：US11348428
申请日：2006-02-06
申请人： Kyoung-Woo Lee , Seung-Man Choi , Ja-Hum Ku , Ki-Chul Park , Sun Kim
发明人： Kyoung-Woo Lee , Seung-Man Choi , Ja-Hum Ku , Ki-Chul Park , Sun Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/31144
摘要： Methods of forming integrated circuit devices include patterning an electrically insulating layer to support dual-damascene interconnect structures therein. The steps of patterning the electrically insulating layer include using multiple planarization layers having different porosity characteristics. Forming an interconnect structure within an integrated circuit device may include forming an electrically insulating layer on a substrate and forming at least one via hole extending at least partially through the electrically insulating layer. The at least one via hole is filled with a first electrically insulating material having a first porosity. The filled at least one via hole is then covered with a second electrically insulating material layer having a second porosity lower than the first porosity. The second electrically insulating material layer is selectively etched back to expose a first portion of the first electrically insulating material in the at least one via hole. The electrically insulating layer is selectively etched to define a trench therein that exposes a second portion of the first electrically insulating material in the at least one via hole. The first electrically insulating material, which has a relatively high degree of porosity, is then removed from the at least one via hole. This removal step may be performed using a relatively mild ashing process because of the high porosity of the first electrically insulating material.
摘要翻译：形成集成电路器件的方法包括图案化电绝缘层以支持其中的双镶嵌互连结构。图案化电绝缘层的步骤包括使用具有不同孔隙特性的多个平坦化层。在集成电路器件内形成互连结构可以包括在衬底上形成电绝缘层，并形成至少部分穿过电绝缘层延伸的至少一个通孔。至少一个通孔填充有具有第一孔隙率的第一电绝缘材料。填充的至少一个通孔然后被具有低于第一孔隙率的第二孔隙率的第二电绝缘材料层覆盖。选择性地回蚀第二电绝缘材料层以暴露至少一个通孔中的第一电绝缘材料的第一部分。电绝缘层被选择性蚀刻以在其中限定其中的沟槽，其暴露出至少一个通孔中的第一电绝缘材料的第二部分。然后从该至少一个通孔去除具有较高孔隙率的第一电绝缘材料。由于第一电绝缘材料的高孔隙率，该去除步骤可以使用相对温和的灰化过程进行。

6. 发明授权

US07365025B2 Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics 有权
标题翻译：使用具有不同孔隙率特性的多个平坦化层在半导体衬底上形成双镶嵌互连结构的方法
公开(公告)号：US07365025B2
公开(公告)日：2008-04-29
申请号：US11348428
申请日：2006-02-06
申请人： Kyoung-Woo Lee , Seung-Man Choi , Ja-Hum Ku , Ki-Chul Park , Sun Oo Kim
发明人： Kyoung-Woo Lee , Seung-Man Choi , Ja-Hum Ku , Ki-Chul Park , Sun Oo Kim
IPC分类号： H01L21/311
CPC分类号： H01L21/76808 , H01L21/31144
摘要： Methods of forming integrated circuit devices include patterning an electrically insulating layer to support dual-damascene interconnect structures therein. The steps of patterning the electrically insulating layer include using multiple planarization layers having different porosity characteristics. Forming an interconnect structure within an integrated circuit device may include forming an electrically insulating layer on a substrate and forming at least one via hole extending at least partially through the electrically insulating layer. The at least one via hole is filled with a first electrically insulating material having a first porosity. The filled at least one via hole is then covered with a second electrically insulating material layer having a second porosity lower than the first porosity. The second electrically insulating material layer is selectively etched back to expose a first portion of the first electrically insulating material in the at least one via hole. The electrically insulating layer is selectively etched to define a trench therein that exposes a second portion of the first electrically insulating material in the at least one via hole.
摘要翻译：形成集成电路器件的方法包括图案化电绝缘层以支持其中的双镶嵌互连结构。图案化电绝缘层的步骤包括使用具有不同孔隙特性的多个平坦化层。在集成电路器件内形成互连结构可以包括在衬底上形成电绝缘层，并形成至少部分穿过电绝缘层延伸的至少一个通孔。至少一个通孔填充有具有第一孔隙率的第一电绝缘材料。填充的至少一个通孔然后被具有低于第一孔隙率的第二孔隙率的第二电绝缘材料层覆盖。选择性地回蚀第二电绝缘材料层以暴露至少一个通孔中的第一电绝缘材料的第一部分。电绝缘层被选择性蚀刻以在其中限定其中的沟槽，其暴露出至少一个通孔中的第一电绝缘材料的第二部分。

7. 发明申请

US20050087784A1 Structure of a CMOS image sensor and method for fabricating the same 有权
标题翻译： CMOS图像传感器的结构及其制造方法
公开(公告)号：US20050087784A1
公开(公告)日：2005-04-28
申请号：US10998803
申请日：2004-11-30
申请人： Soo-Genn Lee , Ki-Chul Park , Kyoung-Woo Lee
发明人： Soo-Genn Lee , Ki-Chul Park , Kyoung-Woo Lee
IPC分类号： G01R31/28 , H01L23/532 , H01L27/146 , H01L31/0224 , H04N17/00 , H01L21/00 , H01L29/768
CPC分类号： H01L23/53238 , G01R31/2829 , H01L21/76805 , H01L27/14603 , H01L27/14623 , H01L27/14627 , H01L27/14636 , H01L27/14687 , H01L31/022408 , H01L2924/0002 , H04N17/002 , H01L2924/00
摘要： An image sensor device and method for forming the same include a photodiode formed in a substrate, at least one electrical interconnection line electrically associated with the photodiode, a light passageway having a light inlet, the light passageway being positioned in alignment with the photodiode, a color filter positioned over the light inlet of the light passageway and a lens positioned over the color filter in alignment with the light passageway wherein the at least one electrical interconnection line includes a copper interconnection formation having a plurality of interlayer dielectric layers in a stacked configuration with a diffusion barrier layer between adjacent interlayer dielectric layers, and a barrier metal layer between the copper interconnection formation and the plurality of interlayer dielectric layers and intervening diffusion barrier layers. An image sensor device may employ copper interconnections if a barrier metal layer is removed from above a photodiode.
摘要翻译：图像传感器装置及其形成方法包括形成在基板中的光电二极管，与光电二极管电连接的至少一个电互连线，具有光入口的光通路，光通路与光电二极管对准，位于光通道的光入口之上的滤色器和位于滤光器上的透镜与光通路对准，其中至少一个电互连线包括铜互连结构，铜互连结构具有层叠形式的多个层间电介质层，相邻的层间电介质层之间的扩散阻挡层和铜互连结构与多个层间电介质层之间的阻挡金属层以及介于其间的扩散阻挡层。如果从光电二极管上方去除阻挡金属层，则图像传感器装置可以采用铜互连。

8. 发明授权

US09015383B2 Method and apparatus for changing input type in input system using universal plug and play 有权
标题翻译：使用通用即插即用改变输入系统输入类型的方法和装置
公开(公告)号：US09015383B2
公开(公告)日：2015-04-21
申请号：US12942605
申请日：2010-11-09
申请人： Je-Young Maeng , Ki-Chul Park , Joo-Yeol Lee , Se-Hee Han
发明人： Je-Young Maeng , Ki-Chul Park , Joo-Yeol Lee , Se-Hee Han
IPC分类号： G06F13/38 , G06F3/00 , H04L29/06 , H04L12/12
CPC分类号： H04L41/0809 , G06F13/4286 , H04L12/12 , H04L12/2809 , H04L12/282 , H04L29/06095 , H04L67/141 , H04L67/16 , H04L67/28 , H04L69/16 , H04L2012/2841 , Y02D50/40
摘要： A method and apparatus for changing an input type in an input system using UPnP are provided. A control point requests input capability information of input devices, which are to perform input and receives the input capability information. The control point sets up a session by determining a receiving device for receiving an input signal and a transmitting device for transmitting the input signal, using the received input capability information. The receiving device receives input data from the transmitting device, and if an input type of the receiving device is changed, the receiving device transmits information about the changed input type to the transmitting device and receives a report descriptor including information about a format of input data according to the changed input type from the transmitting device.
摘要翻译：提供一种用于使用UPnP改变输入系统中的输入类型的方法和装置。控制点请求输入设备的输入能力信息，输入设备信息是执行输入并接收输入能力信息。控制点通过使用接收到的输入能力信息确定用于接收输入信号的接收装置和用于发送输入信号的发送装置来建立会话。接收装置从发送装置接收输入数据，如果改变接收装置的输入类型，则接收装置向发送装置发送关于改变的输入类型的信息，并且接收包括关于输入数据格式的信息的报告描述符根据来自发送装置的改变的输入类型。

9. 发明授权

US10680844B2 Apparatus and method for providing information for a wireless network connection using Wi-Fi 有权
公开(公告)号：US10680844B2
公开(公告)日：2020-06-09
申请号：US12977262
申请日：2010-12-23
申请人： Ji-Hyeok Kim , Joon-Oo Kim , Won-Sang Kwon , Ki-Chul Park
发明人： Ji-Hyeok Kim , Joon-Oo Kim , Won-Sang Kwon , Ki-Chul Park
IPC分类号： G06F15/173 , H04L12/28 , H04L29/12
摘要： An apparatus, method, and system for providing information for a wireless network connection using Wi-Fi. Device information for at least one UPnP device is provided from a plurality of wireless devices including the at least one UPnP device, a device information announcement message including the device information for the at least one UPnP device is generated, and the generated device information announcement message is broadcasted. In this way, information on a UPnP device to which to connect a wireless device is provided in advance, and a user can easily perform a network connection.

10. 发明申请

US20050275005A1 Metal-insulator-metal (MIM) capacitor and method of fabricating the same 有权
标题翻译：金属绝缘体金属（MIM）电容器及其制造方法
公开(公告)号：US20050275005A1
公开(公告)日：2005-12-15
申请号：US11080567
申请日：2005-03-16
申请人： Seung-Man Choi , Ki-Chul Park , Bong-Seok Suh , Il-Ryong Kim
发明人： Seung-Man Choi , Ki-Chul Park , Bong-Seok Suh , Il-Ryong Kim
IPC分类号： H01L21/768 , H01L21/02 , H01L21/3205 , H01L21/822 , H01L21/8234 , H01L23/52 , H01L23/522 , H01L27/04 , H01L27/108 , H01L29/76
CPC分类号： H01L21/76841 , H01L21/76846 , H01L21/7685 , H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： In a MIM capacitor, and method of fabricating the same, the MIM capacitor includes an interlayer insulating layer on a semiconductor substrate, a lower metal interconnection and a lower metal electrode in the interlayer insulating layer, an intermetal dielectric layer covering the lower metal interconnection, the lower metal electrode, and the interlayer insulating layer, a via hole exposing the lower metal interconnection, an upper metal interconnection groove crossing over the via hole, at least one capacitor trench region exposing the lower metal electrode, an upper metal interconnection filling the upper metal interconnection groove, the upper metal interconnection being electrically connected to the lower metal interconnection through the via hole, a dielectric layer covering inner surfaces of the at least one capacitor trench region, and an upper metal electrode surrounded by the dielectric layer to fill the at least one capacitor trench region.
摘要翻译：在MIM电容器及其制造方法中，MIM电容器包括在半导体衬底上的层间绝缘层，层间绝缘层中的下部金属互连和下部金属电极，覆盖下部金属互连的金属间介电层，下金属电极和层间绝缘层，暴露下金属互连的通孔，与通孔相交的上金属互连槽，暴露下金属电极的至少一个电容器沟槽区，填充上金属互连的上金属互连金属互连槽，所述上金属互连通过所述通孔电连接到所述下金属互连，覆盖所述至少一个电容器沟槽区的内表面的电介质层和被所述电介质层包围的上金属电极以填充至少一个电容器沟槽区域。

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