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1. 发明申请

US20070150668A1 MULTI-PATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：多通道可访问的半导体存储器件
公开(公告)号：US20070150668A1
公开(公告)日：2007-06-28
申请号：US11548603
申请日：2006-10-11
申请人： Kyoung-Hwan KWON , Dong-Il SEO , Ho-Cheol LEE , Han-Gu SOHN , Yun-Hee SHIN
发明人： Kyoung-Hwan KWON , Dong-Il SEO , Ho-Cheol LEE , Han-Gu SOHN , Yun-Hee SHIN
IPC分类号： G06F12/00
CPC分类号： G11C7/1075 , G06F13/1663 , G11C8/10 , G11C11/413
摘要： A semiconductor memory device includes ports, data line pairs, where each port associated with one of the data line pairs, sets of address lines, where each port associated with one of the sets of address lines, a shared memory region of a memory cell array, where the shared memory region accessible through the ports, an access controller coupled to the ports and configured to generate an access selection signal in response to a plurality of control signals received through the ports, and an access router coupled to the shared memory region, the data line pairs, and the sets of address lines, the access router configured to selectively couple one of the sets of address lines and one of the data line pairs to the shared memory region in response to the access selection signal.
摘要翻译：半导体存储器件包括端口，数据线对，其中与数据线对之一相关联的每个端口，地址线集合，其中每个端口与地址线中的一组相关联，存储器单元阵列的共享存储器区域，其中所述共享存储器区域可通过所述端口访问，访问控制器耦合到所述端口并且被配置为响应于通过所述端口接收的多个控制信号而生成访问选择信号;以及访问路由器，其耦合到所述共享存储器区域，所述数据线对和所述地址线组，所述接入路由器被配置为响应于所述接入选择信号而选择性地将所述地址线组中的一个和所述数据线对之一耦合到所述共享存储器区域。

2. 发明申请

US20080077937A1 MULTIPATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE WITH HOST INTERFACE BETWEEN PROCESSORS 有权
标题翻译：具有处理器之间主机接口的多路可访问半导体存储器件
公开(公告)号：US20080077937A1
公开(公告)日：2008-03-27
申请号：US11829859
申请日：2007-07-27
申请人： Yun-Hee SHIN , Han-Gu SOHN , Young-Min LEE , Dong-Hyuk LEE , Jong-Wook PARK , Ho-Cheol LEE , Mi-Jo KIM , Jung-Sik KIM , Chang-Ho LEE
发明人： Yun-Hee SHIN , Han-Gu SOHN , Young-Min LEE , Dong-Hyuk LEE , Jong-Wook PARK , Ho-Cheol LEE , Mi-Jo KIM , Jung-Sik KIM , Chang-Ho LEE
IPC分类号： G06F15/167 , G06F9/30
CPC分类号： G11C7/1075 , G11C7/1012 , G11C11/4096
摘要： A multipath accessible semiconductor memory device provides an interface function between processors. The memory device may include a memory cell array having a shared memory area operationally coupled to two or more ports that are independently accessible by two or more processors, an access path forming unit to form a data access path between one of the ports and the shared memory area in response to external signals applied by the processors, and an interface unit having a semaphore area and mailbox areas accessible in the shared memory area by the two or more processors to provide an interface function for communication between the two or more processors.
摘要翻译：多路可及半导体存储器件提供处理器之间的接口功能。存储器设备可以包括具有可操作地耦合到两个或更多个端口的共享存储器区域的存储单元阵列，该两个或多个端口可由两个或多个处理器独立地访问;访问路径形成单元，用于在一个端口和共享之间形成数据访问路径响应于由处理器施加的外部信号的存储区域以及具有信号量区域和由两个或多个处理器在共享存储器区域中可访问的邮箱区域的接口单元，以提供用于两个或多个处理器之间的通信的接口功能。

3. 发明申请

US20090254698A1 MULTI PORT MEMORY DEVICE WITH SHARED MEMORY AREA USING LATCH TYPE MEMORY CELLS AND DRIVING METHOD 失效
标题翻译：具有使用锁存型存储器单元的共享存储区域的多端口存储器件和驱动方法
公开(公告)号：US20090254698A1
公开(公告)日：2009-10-08
申请号：US12392432
申请日：2009-02-25
申请人： Jin-Hyoung KWON , Kyung-Woo NAM , Han-Gu SOHN , Ho-Cheol LEE , Kwang-Myeong JANG
发明人： Jin-Hyoung KWON , Kyung-Woo NAM , Han-Gu SOHN , Ho-Cheol LEE , Kwang-Myeong JANG
IPC分类号： G06F12/00
CPC分类号： G11C11/413 , G11C7/1075
摘要： A multiport semiconductor memory device includes; first and second port units respectively coupled to first and second processors, first and second dedicated memory area accessed by first and second processors, respectively and implemented using DRAM cells, a shared memory area commonly accessed by the first and second processors via respective first and second port units and implemented using memory cells different from the DRAM cells implementing the first and second dedicated memory areas, and a port connection control unit controlling data path configuration between the shared memory area and the first and second port units to enable data communication between the first and second processors through the shared memory area.
摘要翻译：多端口半导体存储器件包括：分别耦合到第一和第二处理器的第一和第二端口单元，分别由第一和第二处理器访问的第一和第二专用存储器区域，并且使用DRAM单元实现;第一和第二处理器通过相应的第一和第二处理器共同访问的共享存储器区域端口单元，并且使用与实现第一和第二专用存储区域的DRAM单元不同的存储器单元来实现，以及端口连接控制单元，其控制共享存储区域与第一和第二端口单元之间的数据路径配置，以使得第一和第二个处理器通过共享内存区域。

4. 发明申请

US20090089545A1 MULTI PROCESSOR SYSTEM HAVING MULTIPORT SEMICONDUCTOR MEMORY WITH PROCESSOR WAKE-UP FUNCTION 失效
标题翻译：具有处理器唤醒功能的多功能半导体存储器的多处理器系统
公开(公告)号：US20090089545A1
公开(公告)日：2009-04-02
申请号：US12235816
申请日：2008-09-23
申请人： Jin-Hyoung KWON , Han-Gu SOHN , Kwang-Myeong JANG
发明人： Jin-Hyoung KWON , Han-Gu SOHN , Kwang-Myeong JANG
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F15/167
摘要： A multiport semiconductor memory device having a processor wake-up function and multiprocessor system employing the same is provided. The multiprocessor system includes: a first processor configured to perform a first predetermined task; a second processor configured to perform a second predetermined task; and a multiport semiconductor memory device coupled to the first processor and the second processor, the multiport semiconductor memory device including: a memory cell array having at least one shared memory area; a first port coupled to the at least one shared memory area; a second port coupled to the at least one shared memory area; and a wake-up signal generator, the first processor being coupled to the at least one shared memory area via the first port, the second processor being coupled to the at least one shared memory area via the second port, the wake-up signal generator being coupled to the first processor and the second processor.
摘要翻译：提供具有处理器唤醒功能的多端口半导体存储器件和采用该多端口半导体存储器件的多处理器系统。多处理器系统包括：第一处理器，被配置为执行第一预定任务; 配置为执行第二预定任务的第二处理器; 以及耦合到所述第一处理器和所述第二处理器的多端口半导体存储器件，所述多端口半导体存储器件包括：具有至少一个共享存储区域的存储单元阵列; 耦合到所述至少一个共享存储器区域的第一端口; 耦合到所述至少一个共享存储区域的第二端口; 以及唤醒信号发生器，所述第一处理器经由所述第一端口耦合到所述至少一个共享存储区域，所述第二处理器经由所述第二端口耦合到所述至少一个共享存储区域，所述唤醒信号发生器耦合到第一处理器和第二处理器。

5. 发明申请

US20090089573A1 MULTI PROCESSOR SYSTEM HAVING DIRECT ACCESS BOOT AND DIRECT ACCESS BOOT METHOD THEREOF 有权
标题翻译：具有直接访问引导和直接访问引导方法的多处理器系统
公开(公告)号：US20090089573A1
公开(公告)日：2009-04-02
申请号：US12211183
申请日：2008-09-16
申请人： Jin-Hyoung KWON , Han-Gu SOHN
发明人： Jin-Hyoung KWON , Han-Gu SOHN
IPC分类号： G06F15/177 , G06F12/02 , G06F12/00
CPC分类号： G06F15/16 , G06F9/4405
摘要： A multiprocessor system having a direct access boot operation and a direct access boot method are provided to substantially reduce a boot error of processor that does not provide a memory link architecture in the multiprocessor system. In an embodiment of the invention, a multiprocessor system includes: a first processor configured to perform a first predetermined task; a second processor configured to perform a second predetermined task; a multiport semiconductor memory device coupled to the first processor and the second processor, the multiport semiconductor memory device including at least one shared memory area, the multiport semiconductor memory device configured to provide access to the at least one shared memory area by the first processor and the second processor; and a non-volatile memory device coupled to the first processor and the second processor, the non-volatile memory device storing a first boot code associated with the first processor and a second boot code associated with the second processor, the multiprocessor system configured to provide the first processor direct access to the non-volatile memory area during a boot operation and indirect access to the non-volatile memory area otherwise.
摘要翻译：提供具有直接访问引导操作和直接访问引导方法的多处理器系统，以显着减少在多处理器系统中不提供存储器链接体系结构的处理器的引导错误。在本发明的一个实施例中，多处理器系统包括：第一处理器，被配置为执行第一预定任务; 配置为执行第二预定任务的第二处理器; 耦合到所述第一处理器和所述第二处理器的多端口半导体存储器件，所述多端口半导体存储器件包括至少一个共享存储器区域，所述多端口半导体存储器件被配置为提供由所述第一处理器访问所述至少一个共享存储器区域;以及第二处理器; 以及耦合到所述第一处理器和所述第二处理器的非易失性存储器件，所述非易失性存储器设备存储与所述第一处理器相关联的第一引导代码和与所述第二处理器相关联的第二引导代码，所述多处理器系统被配置为提供第一处理器在引导操作期间直接访问非易失性存储器区域，而间接访问非易失性存储器区域。

6. 发明申请

US20080256305A1 MULTIPATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：多路可访问的半导体存储器件
公开(公告)号：US20080256305A1
公开(公告)日：2008-10-16
申请号：US12053742
申请日：2008-03-24
申请人： Jin-Hyoung KWON , Han-Gu SOHN , Dong-Woo LEE
发明人： Jin-Hyoung KWON , Han-Gu SOHN , Dong-Woo LEE
IPC分类号： G06F12/02
CPC分类号： G06F15/167 , G06F2212/2022
摘要： A multipath accessible semiconductor memory device provides an interfacing function between multiple processors which indirectly controls a flash memory. The multipath accessible semiconductor memory device comprises a shared memory area, an internal register and a control unit. The shared memory area is accessed by first and second processors through different ports and is allocated to a portion of a memory cell array. The internal register is located outside the memory cell array and is accessed by the first and second processors. The control unit provides storage of address map data associated with the flash memory outside the shared memory area so that the first processor indirectly accesses the flash memory by using the shared memory area and the internal register even when only the second processor is coupled to the flash memory. The control unit also controls a connection path between the shared memory area and one of the first and second processors. The processors share the flash memory and a multiprocessor system is provided that has a compact size, thereby substantially reducing the cost of memory utilized within the multiprocessor system.
摘要翻译：多路可及半导体存储器件提供间接控制闪速存储器的多个处理器之间的接口功能。多路径可访问半导体存储器件包括共享存储区域，内部寄存器和控制单元。共享存储器区域由第一和第二处理器通过不同的端口访问，并被分配给存储单元阵列的一部分。内部寄存器位于存储单元阵列外部，由第一和第二处理器访问。控制单元提供与共享存储器区域之外的闪存相关联的地址映射数据的存储，使得即使当仅第二处理器耦合到闪存时，第一处理器也通过使用共享存储器区域和内部寄存器来间接访问闪速存储器记忆。控制单元还控制共享存储器区域和第一和第二处理器之一之间的连接路径。处理器共享闪存，并提供具有紧凑尺寸的多处理器系统，从而显着降低在多处理器系统内使用的存储器的成本。

7. 发明申请

US20090089487A1 MULTIPORT SEMICONDUCTOR MEMORY DEVICE HAVING PROTOCOL-DEFINED AREA AND METHOD OF ACCESSING THE SAME 审中-公开
标题翻译：具有协议定义区域的多路半导体存储器件及其接收方法
公开(公告)号：US20090089487A1
公开(公告)日：2009-04-02
申请号：US12197472
申请日：2008-08-25
申请人： Jin-Hyoung KWON , Han-Gu SOHN , Kwang-Myeong JANG
发明人： Jin-Hyoung KWON , Han-Gu SOHN , Kwang-Myeong JANG
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F9/544 , G06F12/0851 , G06F12/1045
摘要： A multiprocessor system includes a first processor for performing a first task, a second processor for performing a second task, and a multiport semiconductor memory device having a protocol-defined area for defining a specification related to data communication between the first processor and the second processor. The protocol-defined area is located in at least one shared memory area accessible in common by the first processor and the second processor through a first port and a second port, respectively, and is assigned as a predetermined memory capacity to a portion of a memory cell array.
摘要翻译：多处理器系统包括用于执行第一任务的第一处理器，用于执行第二任务的第二处理器，以及具有用于定义与第一处理器和第二处理器之间的数据通信相关的规范的协议定义区域的多端口半导体存储器件。协议定义的区域位于至少一个共享存储器区域中，第一处理器和第二处理器分别可通过第一端口和第二端口共同访问，并且被分配为存储器的一部分的预定存储器容量单元格阵列。

8. 发明申请

US20080219066A1 MEMORY SYSTEM AND METHOD ENSURING READ DATA STABILITY 失效
标题翻译：记录系统和方法读取数据稳定性
公开(公告)号：US20080219066A1
公开(公告)日：2008-09-11
申请号：US12044174
申请日：2008-03-07
申请人： Young-Min LEE , Han-Gu SOHN
发明人： Young-Min LEE , Han-Gu SOHN
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1072
摘要： A memory system and related method of operation are disclosed. The memory system includes a memory configured to generate a data strobe signal including “(n/2)+1” clock signals, where “n” is a number of base data blocks in read data synchronously transferred by the memory during a read operation, and a memory controller configured to receive the read data, receive the data strobe signal, delay the data strobe signal to generate a delayed data strobe signal, and synchronously output “n/2” sampled data blocks to a requesting device in relation to the delayed data strobe signal.
摘要翻译：公开了一种存储系统及其相关操作方法。存储器系统包括被配置为产生包括“（n / 2）+1”个时钟信号的数据选通信号的存储器，其中“n”是在读取操作期间由存储器同步传送的读取数据中的基本数据块的数量，以及存储器控制器，被配置为接收所读取的数据，接收数据选通信号，延迟数据选通信号以产生延迟的数据选通信号，并且相对于所延迟的数据选通信号同步地将“n / 2”个采样数据块输出到请求设备数据选通信号。

9. 发明申请

US20070022245A1 METHOD OF CONTROLLING REFRESH OPERATION IN MULTI-PORT DRAM AND A MEMORY SYSTEM USING THE METHOD 有权
标题翻译：使用该方法控制多端口DRAM中的刷新操作的方法和存储器系统
公开(公告)号：US20070022245A1
公开(公告)日：2007-01-25
申请号：US11459895
申请日：2006-07-25
申请人： Han-Gu SOHN , Sei-Jin KIM
发明人： Han-Gu SOHN , Sei-Jin KIM
IPC分类号： G06F13/28
CPC分类号： G06F13/1636 , G11C7/1075 , G11C8/12 , G11C8/16 , G11C11/406 , G11C11/40603 , G11C11/40611 , G11C11/40618 , Y02D10/14
摘要： A multi-port memory system includes a shared memory bank, multiple command decoders configured to receive refresh commands from multiple processors, and a refresh controller coupled to the shared memory bank and the command decoders, and configured to selectively apply refresh commands from the command decoders to the shared memory bank.
摘要翻译：多端口存储器系统包括共享存储器组，多个命令解码器，被配置为从多个处理器接收刷新命令;以及刷新控制器，其耦合到共享存储器组和命令解码器，并被配置为选择性地从命令解码器到共享存储器。

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