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1. 发明申请

US20080256305A1 MULTIPATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：多路可访问的半导体存储器件
公开(公告)号：US20080256305A1
公开(公告)日：2008-10-16
申请号：US12053742
申请日：2008-03-24
申请人： Jin-Hyoung KWON , Han-Gu SOHN , Dong-Woo LEE
发明人： Jin-Hyoung KWON , Han-Gu SOHN , Dong-Woo LEE
IPC分类号： G06F12/02
CPC分类号： G06F15/167 , G06F2212/2022
摘要： A multipath accessible semiconductor memory device provides an interfacing function between multiple processors which indirectly controls a flash memory. The multipath accessible semiconductor memory device comprises a shared memory area, an internal register and a control unit. The shared memory area is accessed by first and second processors through different ports and is allocated to a portion of a memory cell array. The internal register is located outside the memory cell array and is accessed by the first and second processors. The control unit provides storage of address map data associated with the flash memory outside the shared memory area so that the first processor indirectly accesses the flash memory by using the shared memory area and the internal register even when only the second processor is coupled to the flash memory. The control unit also controls a connection path between the shared memory area and one of the first and second processors. The processors share the flash memory and a multiprocessor system is provided that has a compact size, thereby substantially reducing the cost of memory utilized within the multiprocessor system.
摘要翻译：多路可及半导体存储器件提供间接控制闪速存储器的多个处理器之间的接口功能。多路径可访问半导体存储器件包括共享存储区域，内部寄存器和控制单元。共享存储器区域由第一和第二处理器通过不同的端口访问，并被分配给存储单元阵列的一部分。内部寄存器位于存储单元阵列外部，由第一和第二处理器访问。控制单元提供与共享存储器区域之外的闪存相关联的地址映射数据的存储，使得即使当仅第二处理器耦合到闪存时，第一处理器也通过使用共享存储器区域和内部寄存器来间接访问闪速存储器记忆。控制单元还控制共享存储器区域和第一和第二处理器之一之间的连接路径。处理器共享闪存，并提供具有紧凑尺寸的多处理器系统，从而显着降低在多处理器系统内使用的存储器的成本。

2. 发明申请

US20090089545A1 MULTI PROCESSOR SYSTEM HAVING MULTIPORT SEMICONDUCTOR MEMORY WITH PROCESSOR WAKE-UP FUNCTION 失效
标题翻译：具有处理器唤醒功能的多功能半导体存储器的多处理器系统
公开(公告)号：US20090089545A1
公开(公告)日：2009-04-02
申请号：US12235816
申请日：2008-09-23
申请人： Jin-Hyoung KWON , Han-Gu SOHN , Kwang-Myeong JANG
发明人： Jin-Hyoung KWON , Han-Gu SOHN , Kwang-Myeong JANG
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F15/167
摘要： A multiport semiconductor memory device having a processor wake-up function and multiprocessor system employing the same is provided. The multiprocessor system includes: a first processor configured to perform a first predetermined task; a second processor configured to perform a second predetermined task; and a multiport semiconductor memory device coupled to the first processor and the second processor, the multiport semiconductor memory device including: a memory cell array having at least one shared memory area; a first port coupled to the at least one shared memory area; a second port coupled to the at least one shared memory area; and a wake-up signal generator, the first processor being coupled to the at least one shared memory area via the first port, the second processor being coupled to the at least one shared memory area via the second port, the wake-up signal generator being coupled to the first processor and the second processor.
摘要翻译：提供具有处理器唤醒功能的多端口半导体存储器件和采用该多端口半导体存储器件的多处理器系统。多处理器系统包括：第一处理器，被配置为执行第一预定任务; 配置为执行第二预定任务的第二处理器; 以及耦合到所述第一处理器和所述第二处理器的多端口半导体存储器件，所述多端口半导体存储器件包括：具有至少一个共享存储区域的存储单元阵列; 耦合到所述至少一个共享存储器区域的第一端口; 耦合到所述至少一个共享存储区域的第二端口; 以及唤醒信号发生器，所述第一处理器经由所述第一端口耦合到所述至少一个共享存储区域，所述第二处理器经由所述第二端口耦合到所述至少一个共享存储区域，所述唤醒信号发生器耦合到第一处理器和第二处理器。

3. 发明申请

US20090254698A1 MULTI PORT MEMORY DEVICE WITH SHARED MEMORY AREA USING LATCH TYPE MEMORY CELLS AND DRIVING METHOD 失效
标题翻译：具有使用锁存型存储器单元的共享存储区域的多端口存储器件和驱动方法
公开(公告)号：US20090254698A1
公开(公告)日：2009-10-08
申请号：US12392432
申请日：2009-02-25
申请人： Jin-Hyoung KWON , Kyung-Woo NAM , Han-Gu SOHN , Ho-Cheol LEE , Kwang-Myeong JANG
发明人： Jin-Hyoung KWON , Kyung-Woo NAM , Han-Gu SOHN , Ho-Cheol LEE , Kwang-Myeong JANG
IPC分类号： G06F12/00
CPC分类号： G11C11/413 , G11C7/1075
摘要： A multiport semiconductor memory device includes; first and second port units respectively coupled to first and second processors, first and second dedicated memory area accessed by first and second processors, respectively and implemented using DRAM cells, a shared memory area commonly accessed by the first and second processors via respective first and second port units and implemented using memory cells different from the DRAM cells implementing the first and second dedicated memory areas, and a port connection control unit controlling data path configuration between the shared memory area and the first and second port units to enable data communication between the first and second processors through the shared memory area.
摘要翻译：多端口半导体存储器件包括：分别耦合到第一和第二处理器的第一和第二端口单元，分别由第一和第二处理器访问的第一和第二专用存储器区域，并且使用DRAM单元实现;第一和第二处理器通过相应的第一和第二处理器共同访问的共享存储器区域端口单元，并且使用与实现第一和第二专用存储区域的DRAM单元不同的存储器单元来实现，以及端口连接控制单元，其控制共享存储区域与第一和第二端口单元之间的数据路径配置，以使得第一和第二个处理器通过共享内存区域。

4. 发明申请

US20090089487A1 MULTIPORT SEMICONDUCTOR MEMORY DEVICE HAVING PROTOCOL-DEFINED AREA AND METHOD OF ACCESSING THE SAME 审中-公开
标题翻译：具有协议定义区域的多路半导体存储器件及其接收方法
公开(公告)号：US20090089487A1
公开(公告)日：2009-04-02
申请号：US12197472
申请日：2008-08-25
申请人： Jin-Hyoung KWON , Han-Gu SOHN , Kwang-Myeong JANG
发明人： Jin-Hyoung KWON , Han-Gu SOHN , Kwang-Myeong JANG
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F9/544 , G06F12/0851 , G06F12/1045
摘要： A multiprocessor system includes a first processor for performing a first task, a second processor for performing a second task, and a multiport semiconductor memory device having a protocol-defined area for defining a specification related to data communication between the first processor and the second processor. The protocol-defined area is located in at least one shared memory area accessible in common by the first processor and the second processor through a first port and a second port, respectively, and is assigned as a predetermined memory capacity to a portion of a memory cell array.
摘要翻译：多处理器系统包括用于执行第一任务的第一处理器，用于执行第二任务的第二处理器，以及具有用于定义与第一处理器和第二处理器之间的数据通信相关的规范的协议定义区域的多端口半导体存储器件。协议定义的区域位于至少一个共享存储器区域中，第一处理器和第二处理器分别可通过第一端口和第二端口共同访问，并且被分配为存储器的一部分的预定存储器容量单元格阵列。

5. 发明申请

US20080313418A1 SEMICONDUCTOR MEMORY DEVICE HAVING PROCESSOR RESET FUNCTION AND RESET CONTROL METHOD THEREOF 有权
标题翻译：具有处理器复位功能的半导体存储器件及其复位控制方法
公开(公告)号：US20080313418A1
公开(公告)日：2008-12-18
申请号：US12140428
申请日：2008-06-17
申请人： Jin-Hyoung KWON , Han-Gu Sohn
发明人： Jin-Hyoung KWON , Han-Gu Sohn
IPC分类号： G06F12/00
CPC分类号： G11C7/1051 , G11C7/1063 , G11C7/1075 , G11C7/22
摘要： A semiconductor memory device for use in a multiprocessor system includes a shared memory area and a reset signal generator. The shared memory area is accessible by the processors of the multiprocessor system through different ports, and is assigned to a portion of a memory cell array. The reset signal generator is configured to provide a reset enable signal to a processor, predetermined as a slave processor among the multiple processors, for a predetermined time after an initial booting of the multiprocessor system. The reset signal generator also provides a reset disable signal to the slave processor after the predetermined time lapses.
摘要翻译：用于多处理器系统的半导体存储器件包括共享存储区域和复位信号发生器。共享存储器区域可由多处理器系统的处理器通过不同端口访问，并被分配给存储单元阵列的一部分。复位信号发生器被配置为在多处理器系统的初始引导之后的预定时间内向处理器提供复位使能信号，预定为多个处理器中的从属处理器。复位信号发生器还在经过预定时间之后向从属处理器提供复位禁止信号。

6. 发明申请

US20090089573A1 MULTI PROCESSOR SYSTEM HAVING DIRECT ACCESS BOOT AND DIRECT ACCESS BOOT METHOD THEREOF 有权
标题翻译：具有直接访问引导和直接访问引导方法的多处理器系统
公开(公告)号：US20090089573A1
公开(公告)日：2009-04-02
申请号：US12211183
申请日：2008-09-16
申请人： Jin-Hyoung KWON , Han-Gu SOHN
发明人： Jin-Hyoung KWON , Han-Gu SOHN
IPC分类号： G06F15/177 , G06F12/02 , G06F12/00
CPC分类号： G06F15/16 , G06F9/4405
摘要： A multiprocessor system having a direct access boot operation and a direct access boot method are provided to substantially reduce a boot error of processor that does not provide a memory link architecture in the multiprocessor system. In an embodiment of the invention, a multiprocessor system includes: a first processor configured to perform a first predetermined task; a second processor configured to perform a second predetermined task; a multiport semiconductor memory device coupled to the first processor and the second processor, the multiport semiconductor memory device including at least one shared memory area, the multiport semiconductor memory device configured to provide access to the at least one shared memory area by the first processor and the second processor; and a non-volatile memory device coupled to the first processor and the second processor, the non-volatile memory device storing a first boot code associated with the first processor and a second boot code associated with the second processor, the multiprocessor system configured to provide the first processor direct access to the non-volatile memory area during a boot operation and indirect access to the non-volatile memory area otherwise.
摘要翻译：提供具有直接访问引导操作和直接访问引导方法的多处理器系统，以显着减少在多处理器系统中不提供存储器链接体系结构的处理器的引导错误。在本发明的一个实施例中，多处理器系统包括：第一处理器，被配置为执行第一预定任务; 配置为执行第二预定任务的第二处理器; 耦合到所述第一处理器和所述第二处理器的多端口半导体存储器件，所述多端口半导体存储器件包括至少一个共享存储器区域，所述多端口半导体存储器件被配置为提供由所述第一处理器访问所述至少一个共享存储器区域;以及第二处理器; 以及耦合到所述第一处理器和所述第二处理器的非易失性存储器件，所述非易失性存储器设备存储与所述第一处理器相关联的第一引导代码和与所述第二处理器相关联的第二引导代码，所述多处理器系统被配置为提供第一处理器在引导操作期间直接访问非易失性存储器区域，而间接访问非易失性存储器区域。

7. 发明申请

US20110035575A1 MULTIPROCESSOR SYSTEM COMPRISING MULTI-PORT SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：包含多端口半导体存储器件的多处理器系统
公开(公告)号：US20110035575A1
公开(公告)日：2011-02-10
申请号：US12780989
申请日：2010-05-17
申请人： Jin-Hyoung KWON
发明人： Jin-Hyoung KWON
IPC分类号： G06F12/02 , G06F9/24 , G06F15/76 , G06F9/02
CPC分类号： G06F15/167 , G06F9/4405
摘要： A multiprocessor system comprises first and second processors connected to a multi-port semiconductor memory device. The multi-port semiconductor memory device comprises a shared memory area and a plurality of mailbox areas used for inter-processor communication. The first and second processors use a single nonvolatile memory device for storing boot data and transmit information for booting via the shared memory area.
摘要翻译：多处理器系统包括连接到多端口半导体存储器件的第一和第二处理器。多端口半导体存储器件包括共享存储器区域和用于处理器间通信的多个邮箱区域。第一和第二处理器使用单个非易失性存储器装置来存储引导数据并且通过共享存储器区域发送用于引导的信息。

8. 发明申请

US20110035537A1 MULTIPROCESSOR SYSTEM HAVING MULTI-COMMAND SET OPERATION AND PRIORITY COMMAND OPERATION 审中-公开
标题翻译：具有多指令集操作和优先命令操作的多处理器系统
公开(公告)号：US20110035537A1
公开(公告)日：2011-02-10
申请号：US12775748
申请日：2010-05-07
申请人： Jin-Hyoung KWON
发明人： Jin-Hyoung KWON
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F15/167
摘要： A multiprocessor system comprises a multi-port semiconductor memory device, a first processor, and a memory link architecture. The multi-port semiconductor memory device comprises a mailbox area and a shared memory area accessible through a plurality of ports. The first processor is configured to write a multi-command set comprising multiple commands for multiple read/write operations to a command area of the shared memory, and to write a message to the mailbox area to indicate the writing of the multi-command set. The memory link architecture comprises a second processor connected to the multi-port semiconductor memory device, and a nonvolatile semiconductor memory device connected to the second processor. The second processor is configured to read the multi-command set from the mailbox area and to sequentially perform the multiple read/write operations according to the multi-command set.
摘要翻译：多处理器系统包括多端口半导体存储器件，第一处理器和存储器链路架构。多端口半导体存储器件包括邮箱区域和可通过多个端口访问的共享存储器区域。第一处理器被配置为向共享存储器的命令区域写入包括用于多个读/写操作的多个命令的多命令集，并将消息写入邮箱区域以指示多命令集的写入。存储器链路架构包括连接到多端口半导体存储器件的第二处理器和连接到第二处理器的非易失性半导体存储器件。第二处理器被配置为从邮箱区域读取多命令集并且根据多命令集顺序执行多个读/写操作。

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