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1. 发明申请

US20100287337A1 NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME 审中-公开
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US20100287337A1
公开(公告)日：2010-11-11
申请号：US12700400
申请日：2010-02-04
申请人： Beom Ju Shin , Kyoung Nam Kim
发明人： Beom Ju Shin , Kyoung Nam Kim
IPC分类号： G06F12/00 , G06F1/04
CPC分类号： G11C16/20 , G11C15/00 , G11C16/10
摘要： A nonvolatile memory device has a memory cell array including a memory cell group for storing option information, and a controller configured to wait for a preset period of time after a command for loading the option information has been received before performing an operation of loading the option information.
摘要翻译：非易失性存储器件具有包括用于存储选项信息的存储单元组的存储单元阵列，以及控制器，被配置为在执行加载选项的操作之前，在接收到用于加载选项信息的命令之后等待预设的时间段信息。

2. 发明授权

US08233334B2 Code address memory (CAM) cell read control circuit of semiconductor memory device and method of reading data of CAM cell 失效
标题翻译：半导体存储器件的代码地址存储器（CAM）单元读取控制电路和读取CAM单元的数据的方法
公开(公告)号：US08233334B2
公开(公告)日：2012-07-31
申请号：US12650980
申请日：2009-12-31
申请人： Kyoung Nam Kim , Beom Ju Shin
发明人： Kyoung Nam Kim , Beom Ju Shin
IPC分类号： G11C7/00
CPC分类号： G11C15/046 , G11C15/00
摘要： A Code Address Memory (CAM) cell read control circuit of a semiconductor memory device includes a CAM cell read circuit configured to read data stored in a CAM cell and to output the read data, an internal delay circuit configured to delay an externally input reset signal and to generate a number of internal command signals, and a signal generation unit configured to generate an internal ready/busy signal in response to the internal command signals. The internal ready/busy signal is generated after the externally input reset signal has reset the CAM cell read circuit.
摘要翻译：半导体存储器件的代码地址存储器（CAM）单元读取控制电路包括：CAM单元读取电路，被配置为读取存储在CAM单元中的数据并输出读取的数据;内部延迟电路，被配置为延迟外部输入的复位信号并且产生多个内部命令信号，以及信号生成单元，被配置为响应于内部命令信号而生成内部就绪/忙信号。内部就绪/忙信号在外部输入复位信号复位CAM单元读取电路后产生。

3. 发明授权

US08437203B2 Nonvolatile memory apparatus and method for processing configuration information thereof 有权
标题翻译：非易失性存储装置及其配置信息的处理方法
公开(公告)号：US08437203B2
公开(公告)日：2013-05-07
申请号：US12983138
申请日：2010-12-31
申请人： Kyoung Nam Kim , Beom Ju Shin
发明人： Kyoung Nam Kim , Beom Ju Shin
IPC分类号： G11C7/00 , G11C8/18
CPC分类号： G11C16/20
摘要： A nonvolatile memory apparatus includes a memory device having a configuration information storage block for storing a first configuration data group and a second configuration data group having fewer bits than the first configuration data group and a configuration information processing circuit configured to determine a majority of the first configuration data group outputted from the memory device, during a first period of a power-up operation, and determine a majority of the second configuration data group outputted from the memory device, during a second period after the first period.
摘要翻译：非易失性存储装置包括存储装置，具有用于存储第一配置数据组的配置信息存储块和比第一配置数据组少的位的第二配置数据组，配置信息处理电路被配置为确定第一配置数据组的大部分配置数据组在上电操作的第一周期期间从存储器件输出，并且在第一周期之后的第二周期期间确定从存储器件输出的大部分第二配置数据组。

4. 发明授权

US08644092B2 Multi-chip package and method of operating the same 有权
标题翻译：多芯片封装和操作方法相同
公开(公告)号：US08644092B2
公开(公告)日：2014-02-04
申请号：US13243223
申请日：2011-09-23
申请人： Kyoung Nam Kim , Beom Ju Shin
发明人： Kyoung Nam Kim , Beom Ju Shin
IPC分类号： G11C7/06
CPC分类号： G11C29/26 , G11C2029/2602
摘要： A semiconductor memory device includes a memory cell array including first memory cells for storing data and second memory cells for storing chip identification (ID) information, a data comparison circuit configured to compare input data and the stored data of the first memory cells and to output comparison data, and output circuits configured to output the comparison data received in parallel from the data comparison circuit. The comparison data is outputted through a selected one of the output circuits according to an enable signal generated based on the chip ID information.
摘要翻译：半导体存储器件包括：存储单元阵列，包括用于存储数据的第一存储器单元和用于存储芯片识别信息的第二存储单元;数据比较电路，用于比较输入数据和第一存储单元的存储数据，并输出比较数据和输出电路，被配置为输出从数据比较电路并行接收的比较数据。根据基于芯片ID信息生成的使能信号，通过选择的一个输出电路输出比较数据。

5. 发明授权

US08344754B2 Multi-chip package 有权
标题翻译：多芯片封装
公开(公告)号：US08344754B2
公开(公告)日：2013-01-01
申请号：US12982544
申请日：2010-12-30
申请人： Kyoung Nam Kim , Beom Ju Shin
发明人： Kyoung Nam Kim , Beom Ju Shin
IPC分类号： H03K17/16 , H03K19/0175 , H03B1/00
CPC分类号： H03K19/00346
摘要： A multi-chip package includes a plurality of chips coupled in parallel to an I/O pad and an output driver circuit included in each of the chips and configured to transmit output data to the I/O pad. The driving force of the output driver circuit is controlled on the basis of stack information indicative of the number of chips being activated.
摘要翻译：多芯片封装包括与I / O焊盘并联耦合的多个芯片和包括在每个芯片中的输出驱动器电路，并被配置为将输出数据发送到I / O焊盘。输出驱动电路的驱动力是根据表示正在激活的芯片数量的堆栈信息进行控制的。

6. 发明授权

US07881109B2 Refresh circuit of semiconductor memory apparatus 失效
标题翻译：半导体存储装置的刷新电路
公开(公告)号：US07881109B2
公开(公告)日：2011-02-01
申请号：US12480962
申请日：2009-06-09
申请人： Kyoung Nam Kim
发明人： Kyoung Nam Kim
IPC分类号： G11C16/04
CPC分类号： G11C11/406 , G11C11/408 , G11C11/4094 , G11C2211/4065
摘要： A refresh circuit of a semiconductor memory apparatus includes a bank active signal generator configured to selectively enable a plurality of bank active signals in response to a piled signal and disable the plurality of bank active signals in response to a plurality of precharge pulses when a refresh signal is enabled; a precharge pulse generator configured to generate a plurality of preliminary precharge pulses in response to the plurality of bank active signals; a delaying unit configured to generate a plurality of preliminary delay precharge pulses by delaying the plurality of preliminary precharge pulses; and a selecting unit configured to selectively output the plurality of preliminary precharge pulses or the plurality of preliminary delay precharge pulses as the plurality of precharge pulses in response to the piled signal.
摘要翻译：半导体存储器装置的刷新电路包括一个存储体有源信号发生器，其被配置为响应堆叠信号有选择地启用多个存储体有效信号，并且当刷新信号时响应于多个预充电脉冲禁用多个存储体有效信号已启用预充电脉冲发生器，被配置为响应于所述多个存储体活动信号而产生多个初步预充电脉冲; 延迟单元，被配置为通过延迟所述多个初步预充电脉冲来产生多个初步延迟预充电脉冲; 以及选择单元，被配置为响应于所述堆叠信号而选择性地输出所述多个预充电脉冲或所述多个预备延迟预充电脉冲作为所述多个预充电脉冲。

7. 发明申请

US20100033218A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：半导体集成电路及其控制方法
公开(公告)号：US20100033218A1
公开(公告)日：2010-02-11
申请号：US12333173
申请日：2008-12-11
申请人： Kyoung Nam Kim
发明人： Kyoung Nam Kim
IPC分类号： H03L7/06
CPC分类号： G11C8/18 , H03L7/0812
摘要： A semiconductor integrated circuit includes a DLL controlling block configured to enable or disable an update enable signal by detecting a change in a voltage level of a phase detecting signal during a predetermined time when an operation enable signal and a threshold phase difference detecting signal are enabled, and a delay locked loop (DLL) circuit configured to generate an output clock signal by delaying and driving the reference clock signal and to control a frequency of a change in the delay amount of the reference clock signal in response to the update enable signal.
摘要翻译：半导体集成电路包括DLL控制块，其被配置为通过在使能使能信号和阈值相位差检测信号被使能的预定时间期间检测相位检测信号的电压电平的变化来启用或禁用更新使能信号，以及延迟锁定环（DLL）电路，被配置为通过延迟和驱动参考时钟信号来产生输出时钟信号，并且响应于更新使能信号控制参考时钟信号的延迟量的变化的频率。

8. 发明授权

US07746073B2 Magnetic resonance imaging system 有权
标题翻译：磁共振成像系统
公开(公告)号：US07746073B2
公开(公告)日：2010-06-29
申请号：US12046209
申请日：2008-03-11
申请人： Zang Hee Cho , Young Bo Kim , Kyoung Nam Kim , Suk Min Hong
发明人： Zang Hee Cho , Young Bo Kim , Kyoung Nam Kim , Suk Min Hong
IPC分类号： G01V3/00
CPC分类号： G01R33/34046 , G01R33/34069 , G01R33/3415
摘要： A magnetic resonance imaging system is provided, which can provide the homogeneous magnetic field to obtain a head anatomic image with a high resolution and high SNR by coaxially disposing a receive-only phased array antenna inside a transmit-only antenna with a predetermined gap, and thereby a detailed and accurate image of a man's head can be obtained. In the present invention, the system comprises: a transmit-only antenna comprising at least two saddle quadrature antennas connected with each other to form a ring shape, one of the connections being a joint and the remaining connections being formed in an overlapping fashion; and a receive-only phased array antenna comprising a plurality of receive-only antennas connected with each other to form a ring shape, one of the connections being a joint and the remaining connections being formed in an overlapping fashion, wherein an inner diameter of the receive-only phased array antenna is shorter than that of the transmit-only antenna, and the receive-only phased array antenna is coaxially disposed inside the transmit-only antenna with a predetermined gap.
摘要翻译：提供一种磁共振成像系统，其可以提供均匀的磁场以通过在仅具有预定间隙的仅发射天线内同轴地布置仅接收相位阵列天线来获得具有高分辨率和高SNR的头部解剖图像，以及从而可以获得人的头部的详细和准确的图像。在本发明中，该系统包括：包括至少两个彼此连接的鞍形正交天线以形成环形的仅发射天线，其中一个连接是接头，其余连接以重叠的方式形成; 以及接收相位阵列天线，其包括彼此连接以形成环形的多个仅接收天线，所述连接中的一个是接头，并且所述剩余连接以重叠的方式形成，其中，只接收相位阵列天线短于仅发射天线的天线，并且仅接收相位阵列天线以预定间隙同轴地布置在仅发射天线内。

9. 发明授权

US07733088B2 MRI system RF coil assembly with a birdcage transmit only coil and a pseudo-chain-link receive only coil array 失效
标题翻译： MRI系统RF线圈组件与鸟笼只传输线圈和伪链接接收线圈阵列
公开(公告)号：US07733088B2
公开(公告)日：2010-06-08
申请号：US12177653
申请日：2008-07-22
申请人： Zang Hee Cho , Young Bo Kim , Kyoung Nam Kim , Suk Min Hong
发明人： Zang Hee Cho , Young Bo Kim , Kyoung Nam Kim , Suk Min Hong
IPC分类号： G01V3/00 , A61B5/055
CPC分类号： G01R33/34046 , G01R33/3415
摘要： There is provided an RF (radio frequency) coil assembly of a magnetic resonance imaging (MRI) system, which comprises a birdcage transmit-only coil using inhomogeneous modes. Further, a multi-channel receive-only phased array coil is provided. In one embodiment, the multi-channel receive-only phased array coil may include a plurality of ring-shaped receive-only coils, wherein the receive-only coils are connected to each other in a pseudo-chain-link configuration to form a ring shape. The multi-channel receive-only phased array coil may be located inside said transmit-only coil and spaced a predetermined distance apart therefrom. In accordance with the embodiments, emphasis images of the peripheral part of a human brain with high resolution and high signal to noise ratio may be obtained.
摘要翻译：提供了一种磁共振成像（MRI）系统的RF（射频）线圈组件，其包括使用不均匀模式的鸟笼发射线圈。此外，提供了多通道接收相控阵列线圈。在一个实施例中，多通道接收相位阵列线圈可以包括多个环形接收线圈，其中仅接收线圈以伪链接配置彼此连接以形成环形状。多通道接收相位阵列线圈可以位于所述发射线圈内并与之隔开预定距离。根据实施例，可以获得具有高分辨率和高信噪比的人脑周边部分的强调图像。

10. 发明授权

US07982511B2 DLL circuit and method of controlling the same 有权
标题翻译： DLL电路及其控制方法
公开(公告)号：US07982511B2
公开(公告)日：2011-07-19
申请号：US11647379
申请日：2006-12-29
申请人： Kyoung Nam Kim
发明人： Kyoung Nam Kim
IPC分类号： H03L7/06
CPC分类号： H03L7/0812
摘要： A delayed lock loop (DLL) circuit includes: a phase conversion control unit configured to latch an initial value of a phase comparison signal, and output the latched signal as a phase conversion control signal. A phase converting unit configured to control the phase of a delay clock on the basis of the phase conversion control signal, and transmit the controlled delay clock to a delay compensating unit.
摘要翻译：延迟锁定环路（DLL）电路包括：相位转换控制单元，被配置为锁存相位比较信号的初始值，并输出锁存信号作为相位转换控制信号。相位转换单元，被配置为基于相位转换控制信号来控制延迟时钟的相位，并将受控延迟时钟发送到延迟补偿单元。

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