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1. 发明授权

US08823113B2 Gate electrode and gate contact plug layouts for integrated circuit field effect transistors 有权
标题翻译：用于集成电路场效应晶体管的栅电极和栅极接触插头布局
公开(公告)号：US08823113B2
公开(公告)日：2014-09-02
申请号：US12984762
申请日：2011-01-05
申请人： Kyo-Suk Chae , Satoru Yamada , Sang-Yeon Han , Young-Jin Choi , Wook-Je Kim
发明人： Kyo-Suk Chae , Satoru Yamada , Sang-Yeon Han , Young-Jin Choi , Wook-Je Kim
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L23/535 , H01L27/0207 , H01L29/0649 , H01L29/0847 , H01L29/42376 , H01L29/4238 , H01L29/4933 , H01L29/7833
摘要： A four transistor layout can include an isolation region that defines an active region, the active region extending along first and second different directions. A common source region of the four transistors extends from a center of the active region along both the first and second directions to define four quadrants of the active region that are outside the common source region. Four drain regions are provided, a respective one of which is in a respective one of the four quadrants and spaced apart from the common source region. Finally, four gate electrodes are provided, a respective one of which is in a respective one of the four quadrants between the common source region and a respective one of the four drain regions. A respective gate electrode includes a vertex and first and second extending portions, the first extending portions extending from the vertex along the first direction and the second extending portions extending from the vertex along the second direction.
摘要翻译：四晶体管布局可以包括限定有源区域的隔离区域，有源区域沿第一和第二不同方向延伸。四个晶体管的共同源极区域从有源区域的中心沿着第一和第二方向延伸，以限定位于公共源极区域外的有源区域的四个象限。设置四个漏极区，其中的一个位于四个象限中的相应一个中并与公共源极区间隔开。最后，提供四个栅电极，其中的一个位于公共源极区域和四个漏极区域中的相应一个之间的四个象限中的相应一个中。相应的栅电极包括顶点和第一和第二延伸部分，第一延伸部分从顶点沿着第一方向延伸，第二延伸部分从顶点沿着第二方向延伸。

2. 发明申请

US20120001271A1 GATE ELECTRODE AND GATE CONTACT PLUG LAYOUTS FOR INTEGRATED CIRCUIT FIELD EFFECT TRANSISTORS 有权
标题翻译：门电极和门接触电路集成电路场效应晶体管
公开(公告)号：US20120001271A1
公开(公告)日：2012-01-05
申请号：US12984762
申请日：2011-01-05
申请人： Kyo-Suk Chae , Satoru Yamada , Sang-Yeon Han , Young-Jin Choi , Wook-Je Kim
发明人： Kyo-Suk Chae , Satoru Yamada , Sang-Yeon Han , Young-Jin Choi , Wook-Je Kim
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L23/535 , H01L27/0207 , H01L29/0649 , H01L29/0847 , H01L29/42376 , H01L29/4238 , H01L29/4933 , H01L29/7833
摘要： A four transistor layout can include an isolation region that defines an active region, the active region extending along first and second different directions. A common source region of the four transistors extends from a center of the active region along both the first and second directions to define four quadrants of the active region that are outside the common source region. Four drain regions are provided, a respective one of which is in a respective one of the four quadrants and spaced apart from the common source region. Finally, four gate electrodes are provided, a respective one of which is in a respective one of the four quadrants between the common source region and a respective one of the four drain regions. A respective gate electrode includes a vertex and first and second extending portions, the first extending portions extending from the vertex along the first direction and the second extending portions extending from the vertex along the second direction.
摘要翻译：四晶体管布局可以包括限定有源区域的隔离区域，有源区域沿第一和第二不同方向延伸。四个晶体管的共同源极区域从有源区域的中心沿着第一和第二方向延伸，以限定位于公共源极区域外的有源区域的四个象限。设置四个漏极区，其中的一个位于四个象限中的相应一个中并与公共源极区间隔开。最后，提供四个栅电极，其中的一个位于公共源极区域和四个漏极区域中的相应一个之间的四个象限中的相应一个中。相应的栅电极包括顶点和第一和第二延伸部分，第一延伸部分从顶点沿着第一方向延伸，第二延伸部分从顶点沿着第二方向延伸。

3. 发明授权

US09418988B2 Gate electrode and gate contact plug layouts for integrated circuit field effect transistors 有权
标题翻译：用于集成电路场效应晶体管的栅电极和栅极接触插头布局
公开(公告)号：US09418988B2
公开(公告)日：2016-08-16
申请号：US14461202
申请日：2014-08-15
申请人： Kyo-Suk Chae , Satoru Yamada , Sang-Yeon Han , Young-Jin Choi , Wook-Je Kim
发明人： Kyo-Suk Chae , Satoru Yamada , Sang-Yeon Han , Young-Jin Choi , Wook-Je Kim
IPC分类号： H01L27/088 , H01L29/423 , H01L29/78
CPC分类号： H01L27/088 , H01L23/535 , H01L27/0207 , H01L29/0649 , H01L29/0847 , H01L29/42376 , H01L29/4238 , H01L29/4933 , H01L29/7833
摘要： A four transistor layout can include an isolation region that defines an active region, the active region extending along first and second different directions. A common source region of the four transistors extends from a center of the active region along both the first and second directions to define four quadrants of the active region that are outside the common source region. Four drain regions are provided, a respective one of which is in a respective one of the four quadrants and spaced apart from the common source region. Finally, four gate electrodes are provided, a respective one of which is in a respective one of the four quadrants between the common source region and a respective one of the four drain regions. A respective gate electrode includes a vertex and first and second extending portions, the first extending portions extending from the vertex along the first direction and the second extending portions extending from the vertex along the second direction.
摘要翻译：四晶体管布局可以包括限定有源区域的隔离区域，有源区域沿第一和第二不同方向延伸。四个晶体管的共同源极区域从有源区域的中心沿着第一和第二方向延伸，以限定位于公共源极区域外的有源区域的四个象限。设置四个漏极区，其中的一个位于四个象限中的相应一个中并与公共源极区间隔开。最后，提供四个栅电极，其中的一个位于公共源极区域和四个漏极区域中的相应一个之间的四个象限中的相应一个中。相应的栅电极包括顶点和第一和第二延伸部分，第一延伸部分从顶点沿着第一方向延伸，第二延伸部分从顶点沿着第二方向延伸。

4. 发明授权

US08653622B2 Semiconductor device including transistor and fuse circuit and semiconductor module including the same 有权
标题翻译：包括晶体管和熔丝电路的半导体器件和包括其的半导体模块
公开(公告)号：US08653622B2
公开(公告)日：2014-02-18
申请号：US13038117
申请日：2011-03-01
申请人： Woo-Song Ahn , Satoru Yamada , Young-Jin Choi , Seung-Uk Han , Kyo-Suk Chae
发明人： Woo-Song Ahn , Satoru Yamada , Young-Jin Choi , Seung-Uk Han , Kyo-Suk Chae
IPC分类号： H01L29/792 , H01L23/525
CPC分类号： H01L29/792 , H01L21/28273 , H01L21/28282 , H01L23/5256 , H01L27/105 , H01L27/10897 , H01L27/11526 , H01L27/11573 , H01L29/42336 , H01L29/42352 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, a first node impurity region, a second node impurity region, a third node impurity region, and an insulating layer. The first through third node impurity regions are disposed in the semiconductor substrate. Each of the first through third node impurity regions has a longitudinal length, a transverse length and a thickness respectively corresponding to first through third directions, which are perpendicular with respect to each other. The first node impurity region is parallel to the second and third node impurity regions, which are disposed in the substantially same line. The insulating layer is located between the first through third node impurity regions in the semiconductor substrate.
摘要翻译：公开了一种半导体器件。半导体器件包括半导体衬底，第一晶体杂质区，第二晶体杂质区，第三晶体杂质区和绝缘层。第一至第三晶体杂质区设置在半导体衬底中。第一至第三节点杂质区域中的每一个具有分别相对于彼此垂直的第一至第三方向的纵向长度，横向长度和厚度。第一节点杂质区域平行于第二和第三节点杂质区域，其被布置在基本相同的线上。绝缘层位于半导体衬底中的第一至第三结点杂质区之间。

5. 发明申请

US20110241099A1 SEMICONDUCTOR DEVICE INCLUDING TRANSISTOR AND FUSE CIRCUIT AND SEMICONDUCTOR MODULE INCLUDING THE SAME 有权
标题翻译：包括晶体管和保险丝电路的半导体器件和包括其的半导体器件
公开(公告)号：US20110241099A1
公开(公告)日：2011-10-06
申请号：US13038117
申请日：2011-03-01
申请人： Woo-Song Ahn , Satoru Yamada , Young-Jin Choi , Seung-Uk Han , Kyo-Suk Chae
发明人： Woo-Song Ahn , Satoru Yamada , Young-Jin Choi , Seung-Uk Han , Kyo-Suk Chae
IPC分类号： H01L29/792 , H01L23/525
CPC分类号： H01L29/792 , H01L21/28273 , H01L21/28282 , H01L23/5256 , H01L27/105 , H01L27/10897 , H01L27/11526 , H01L27/11573 , H01L29/42336 , H01L29/42352 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, a first node impurity region, a second node impurity region, a third node impurity region, and an insulating layer. The first through third node impurity regions are disposed in the semiconductor substrate. Each of the first through third node impurity regions has a longitudinal length, a transverse length and a thickness respectively corresponding to first through third directions, which are perpendicular with respect to each other. The first node impurity region is parallel to the second and third node impurity regions, which are disposed in the substantially same line. The insulating layer is located between the first through third node impurity regions in the semiconductor substrate.
摘要翻译：公开了一种半导体器件。半导体器件包括半导体衬底，第一晶体杂质区，第二晶体杂质区，第三晶体杂质区和绝缘层。第一至第三晶体杂质区设置在半导体衬底中。第一至第三节点杂质区域中的每一个具有分别相对于彼此垂直的第一至第三方向的纵向长度，横向长度和厚度。第一节点杂质区域平行于第二和第三节点杂质区域，其被布置在基本相同的线上。绝缘层位于半导体衬底中的第一至第三结点杂质区之间。

6. 发明申请

US20120142160A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING DEUTERIUM ANNEALING 有权
标题翻译：使用真空退火法制造半导体器件的方法
公开(公告)号：US20120142160A1
公开(公告)日：2012-06-07
申请号：US13216706
申请日：2011-08-24
申请人： Seung-Uk Han , Nam-Ho Jeon , Satoru Yamada , Young-Jin Choi
发明人： Seung-Uk Han , Nam-Ho Jeon , Satoru Yamada , Young-Jin Choi
IPC分类号： H01L21/02 , H01L21/28
CPC分类号： H01L27/10894 , H01L21/28176 , H01L21/3003 , H01L27/10808 , H01L27/10852
摘要： A method of fabricating a semiconductor device is disclosed, the method generally including the steps of: forming a gate dielectric layer on a semiconductor substrate;forming a gate electrode on the gate dielectric layer;forming an etch stop layer on the gate electrode;forming a capacitor on the semiconductor substrate adjacent to the gate electrode;after forming the capacitor, forming a contact hole passing through the etch stop layer on the gate electrode;and, diffusing deuterium into the gate dielectric layer through the contact hole.
摘要翻译：公开了一种制造半导体器件的方法，所述方法通常包括以下步骤：在半导体衬底上形成栅极电介质层;在栅极电介质层上形成栅电极;在栅电极上形成蚀刻停止层; 在形成电容器之后形成穿过栅电极上的蚀刻停止层的接触孔;以及通过接触孔将氘扩散到栅介质层中。

7. 发明授权

US08669165B2 Method of fabricating semiconductor device using deuterium annealing 有权
标题翻译：使用氘退火制造半导体器件的方法
公开(公告)号：US08669165B2
公开(公告)日：2014-03-11
申请号：US13216706
申请日：2011-08-24
申请人： Seung-Uk Han , Nam-Ho Jeon , Satoru Yamada , Young-Jin Choi
发明人： Seung-Uk Han , Nam-Ho Jeon , Satoru Yamada , Young-Jin Choi
IPC分类号： H01L21/02
CPC分类号： H01L27/10894 , H01L21/28176 , H01L21/3003 , H01L27/10808 , H01L27/10852
摘要： A method of fabricating a semiconductor device is disclosed, the method generally including the steps of: forming a gate dielectric layer on a semiconductor substrate; forming a gate electrode on the gate dielectric layer; forming an etch stop layer on the gate electrode; forming a capacitor on the semiconductor substrate adjacent to the gate electrode; after forming the capacitor, forming a contact hole passing through the etch stop layer on the gate electrode; and, diffusing deuterium into the gate dielectric layer through the contact hole.
摘要翻译：公开了制造半导体器件的方法，该方法通常包括以下步骤：在半导体衬底上形成栅介质层; 在所述栅极电介质层上形成栅电极; 在栅电极上形成蚀刻停止层; 在与栅电极相邻的半导体衬底上形成电容器; 在形成电容器之后，形成穿过栅电极上的蚀刻停止层的接触孔; 并且通过接触孔将氘扩散到栅极电介质层中。

8. 发明申请

US20120153404A1 ANTI-FUSE DEVICE AND SEMICONDUCTOR DEVICE AND SYSTEM INCLUDING THE SAME 有权
标题翻译：抗保护装置和半导体装置及包括其的系统
公开(公告)号：US20120153404A1
公开(公告)日：2012-06-21
申请号：US13328097
申请日：2011-12-16
申请人： Woo-song AHN , Satoru YAMADA , Young-Jin Choi
发明人： Woo-song AHN , Satoru YAMADA , Young-Jin Choi
IPC分类号： H01L29/78
CPC分类号： H01L23/5252 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse device includes a gate electrode on a semiconductor substrate, a gate insulating layer between the semiconductor substrate and the gate electrode, junction regions in the semiconductor substrate adjacent the gate electrode, and at least one anti-breakdown material layer between the junction regions, the gate insulating layer being between the gate electrode and the anti-breakdown material layer.
摘要翻译：反熔丝器件包括半导体衬底上的栅电极，半导体衬底和栅电极之间的栅极绝缘层，与栅电极相邻的半导体衬底中的接合区域，以及至少一个在该连接点之间的抗击穿材料层区域，栅极绝缘层位于栅电极和抗分解材料层之间。

9. 发明授权

US08487999B2 Apparatus for measurement of surface profile 有权
标题翻译：用于测量表面轮廓的装置
公开(公告)号：US08487999B2
公开(公告)日：2013-07-16
申请号：US12598578
申请日：2009-03-30
申请人： Young-Woong Yoo , Young-Jin Choi , Cheol-Hoon Cho
发明人： Young-Woong Yoo , Young-Jin Choi , Cheol-Hoon Cho
IPC分类号： H04N7/18
CPC分类号： G01B11/24 , G01B11/2509 , G01N21/956 , G01N2021/95638
摘要： The present invention relates to an apparatus for measurement of the surface profile detecting 2D-image of the surface of the object. The apparatus for measurement of the surface profile according to the present invention comprises a first light source illuminating a first one-color light to the surface of the object; a second light source illuminating a second one-color light of which color is different from the first one-color light to the surface of the object; a black-and-white camera capturing the first one-color light and the second one-color light reflected from the surface of the object, which are illuminated from the first light source and the second light source; and a controller controlling the first light source, the second light source and the black-and-white camera to obtain a first black-and-white image data and a second black-and-white image data corresponding to the first one-color light and the second one-color light respectively in the state that the first one-color light and the second one-color light are illuminated to the surface of the object, and generating a synthesized color image of the surface of the object using the first black-and-white image data and the second black-and-white image data. Thus, it is possible to obtain the color 2D-image using the low-priced black-and-white camera, and it is also possible to improve processing speed by means of using the black-and-white camera of which processing speed is faster than that of a color camera.
摘要翻译：本发明涉及一种用于测量物体表面的表面轮廓检测2D图像的装置。根据本发明的用于测量表面轮廓的装置包括将第一单色光照射到物体的表面的第一光源; 第二光源，其将颜色与第一单色光不同的第二单色光照射到物体的表面; 捕获从第一光源和第二光源照射的从物体的表面反射的第一单色光和第二单色光的黑白照相机; 以及控制器，控制第一光源，第二光源和黑白相机，以获得与第一单色光对应的第一黑白图像数据和第二黑白图像数据和第二单色光分别在第一单色光和第二单色光被照射到被摄体的表面的状态下，并且使用第一黑色产生对象的表面的合成彩色图像白色图像数据和第二黑白图像数据。因此，可以使用低价黑白相机获得彩色2D图像，并且还可以通过使用处理速度更快的黑白相机来提高处理速度比彩色相机。

10. 发明申请

US20110236599A1 Plasma processing including asymmetrically grounding a susceptor 有权
标题翻译：等离子体处理包括不对称接地的感受器
公开(公告)号：US20110236599A1
公开(公告)日：2011-09-29
申请号：US13153641
申请日：2011-06-06
申请人： Gaku Furuta , Soo Young Choi , Young-Jin Choi
发明人： Gaku Furuta , Soo Young Choi , Young-Jin Choi
IPC分类号： C23C16/509 , C23C16/455 , C23C16/458
CPC分类号： C23C16/4585 , C23C16/45565 , C23C16/5096 , H01J37/32091 , H01J37/32568 , H01J37/32577 , H01J37/32623 , H01J37/32697
摘要： An asymmetrically grounded susceptor used in a plasma processing chamber for chemical vapor deposition onto large rectangular panels supported on and grounded by the susceptor. A plurality of grounding straps are connected between the periphery of the susceptor to the grounded vacuum chamber to shorten the grounding paths for RF electrons. Flexible straps allow the susceptor to vertically move. The straps provide a conductance to ground which is asymmetric around the periphery. The straps may be evenly spaced but have different thicknesses or different shapes or be removed from available grounding point and hence provide different RF conductances. The asymmetry is selected to improve the deposition uniformity and other qualities of the PECVD deposited film.
摘要翻译：用于等离子体处理室中的不对称接地的基座，用于化学气相沉积到由基座支撑并接地的大矩形面板上。多个接地带连接在基座的外围与接地的真空室之间，以缩短RF电子的接地路径。柔性带允许基座垂直移动。带子提供对周边不对称的地面电导。带可以是均匀间隔的，但是具有不同的厚度或不同的形状，或者从可用的接地点去除并因此提供不同的RF电导。选择不对称性以改善PECVD沉积膜的沉积均匀性和其他质量。

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