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1. 发明申请

US20050281266A1 Human readable and writable addressing method in a home network protocol 审中-公开
标题翻译：家庭网络协议中的人类可读写的寻址方法
公开(公告)号：US20050281266A1
公开(公告)日：2005-12-22
申请号：US11024782
申请日：2004-12-30
申请人： Kwangsoon Choi , Kwangmo Jung , Woong Choi
发明人： Kwangsoon Choi , Kwangmo Jung , Woong Choi
IPC分类号： H04L12/28 , H04L12/66 , H04L29/12
CPC分类号： H04L29/12066 , H04L29/12594 , H04L61/1511 , H04L61/30
摘要： A human readable and writable addressing method in a home network is disclosed. A disclosed method comprises inputting a URL type, inputting the address of a gateway server, and inputting a device indicator.
摘要翻译：公开了一种家庭网络中的人类可读写的寻址方法。所公开的方法包括输入URL类型，输入网关服务器的地址以及输入设备指示符。

2. 发明申请

US20090162570A1 APPARATUS AND METHOD FOR PROCESSING A SUBSTRATE USING INDUCTIVELY COUPLED PLASMA TECHNOLOGY 审中-公开
标题翻译：使用电感耦合等离子体技术处理基板的装置和方法
公开(公告)号：US20090162570A1
公开(公告)日：2009-06-25
申请号：US11960111
申请日：2007-12-19
申请人： Johanes F. Swenberg , Wei Liu , Hanh D. Nguyen , Son T. Nguyen , Roger Curtis , Philip A. Bottini , Michael J. Mark , Theresa Kramer Guarini , Woong Choi
发明人： Johanes F. Swenberg , Wei Liu , Hanh D. Nguyen , Son T. Nguyen , Roger Curtis , Philip A. Bottini , Michael J. Mark , Theresa Kramer Guarini , Woong Choi
IPC分类号： H05H1/24 , C23C16/503
CPC分类号： H01J37/321 , H01J37/3211 , H01J37/32174
摘要： The present invention generally provides apparatus and methods for processing a semiconductor substrate. Particularly, the present invention provides an inductively coupled plasma reactor having improved process uniformity. One embodiment of the present invention provides an apparatus for processing a substrate comprising a chamber body defining a process volume configured to process the substrate therein, an adjustable coil assembly coupled to the chamber body outside the process volume, a supporting pedestal disposed in the process volume and configured to support the substrate therein, and a gas injection assembly configured to supply a process gas towards a first process zone and a second process zone independently.
摘要翻译：本发明通常提供了用于处理半导体衬底的装置和方法。特别地，本发明提供了具有改进的工艺均匀性的电感耦合等离子体反应器。本发明的一个实施例提供了一种用于处理衬底的装置，其包括限定被配置为在其中处理衬底的处理体积的室主体，耦合到处理体积外部的室主体的可调节线圈组件，设置在处理体积中的支撑座并且被配置为在其中支撑衬底;以及气体注入组件，其构造成独立地朝向第一处理区域和第二处理区域提供处理气体。

3. 外观设计

USD568859S1 Cellular phone 有权
公开(公告)号：USD568859S1
公开(公告)日：2008-05-13
申请号：US29274669
申请日：2007-05-14
申请人： Woong Choi
设计人： Woong Choi

4. 发明申请

US20070155609A1 Composition of paste, green sheet for barrier ribs of plasma display panel, and plasma display panel using the same 审中-公开
标题翻译：浆料的组成，等离子体显示面板的隔壁的生片，以及使用其的等离子体显示面板
公开(公告)号：US20070155609A1
公开(公告)日：2007-07-05
申请号：US11435923
申请日：2006-05-18
申请人： Woong Choi
发明人： Woong Choi
IPC分类号： C03C8/16 , C03C14/00
CPC分类号： C03C8/14 , C03C17/008 , C03C17/04 , C03C17/3411 , C03C2217/452 , C03C2217/475 , C03C2218/33 , C03C2218/355 , H01J9/242 , H01J11/12 , H01J11/36 , H01J2211/366
摘要： A composition of paste and a green sheet for forming double-layered barrier ribs for use in PDPs, and the PDPs using the same is provided. A composition of paste for use in barrier ribs in PDPs comprises about 30 wt % to 60 wt % of a Pb-free glass powder, about 1 wt % to 10 wt % of a filler, about 10 wt % to 30 wt % of a binder, about 1 wt % to 8 wt %/o of a plasticizer, about 0.1 wt % to 3 wt % of a dispersing agent, and about 15 wt % to 35 wt % of a solvent. The PDPs comprises a lower substrate and a upper substrate oppositely disposed each other, address electrodes formed on the lower substrate, and discharge electrodes formed on the upper substrate, barrier ribs disposed in the area between the lower substrate and the upper substrate to divide a plurality of discharge cells, and a red, green and blue fluorescent substance layer formed in the discharge cell divided by the barrier ribs. The barrier ribs are formed by a paste composition comprising about 30 wt % to 60 wt % of a Pb-free glass powder, about 1 wt % to 10 wt % of a filler, about 10 wt % to 30 wt % of a binder, about 1 wt % to 8 wt % of a plasticizer, about 0.1 wt % to 3 wt % of a dispersing agent and about 15 wt % to 35 wt % of a solvent.
摘要翻译：提供了一种用于形成用于PDP的双层障壁的糊状组合物和生片，以及使用它们的PDP。用于PDP中的隔壁的糊剂组合物包含约30重量％至60重量％的无铅玻璃粉末，约1重量％至10重量％的填料，约10重量％至30重量％的约1重量％至8重量％的增塑剂，约0.1重量％至3重量％的分散剂和约15重量％至35重量％的溶剂。 PDP包括下基板和彼此相对布置的上基板，形成在下基板上的寻址电极和形成在上基板上的放电电极，设置在下基板和上基板之间的区域中的多个分隔多个的放电单元，以及形成在由隔壁分隔的放电单元中的红色，绿色和蓝色荧光体层。阻挡肋由包含约30重量％至60重量％的无铅玻璃粉末，约1重量％至10重量％的填料，约10重量％至30重量％的粘合剂的糊料组合物形成，约1重量％至8重量％的增塑剂，约0.1重量％至3重量％的分散剂和约15重量％至35重量％的溶剂。

5. 发明申请

US20060001792A1 Thin film transistor array substrate, display using the same, and fabrication method thereof 有权
标题翻译：薄膜晶体管阵列基板，使用其的显示器及其制造方法
公开(公告)号：US20060001792A1
公开(公告)日：2006-01-05
申请号：US11159111
申请日：2005-06-23
申请人： Woong Choi
发明人： Woong Choi
IPC分类号： G02F1/1333
CPC分类号： H01L27/3223 , G02F1/13458 , G02F2001/136254 , H01L27/12 , H01L27/156 , H01L27/3244 , H01L27/3246 , H01L27/3276 , H01L51/5253
摘要： A display and a method of manufacturing the same, including a substrate including an image displaying part comprising a plurality of pixels, a dummy testing pad, and a first insulating layer covering the dummy testing pad.
摘要翻译：一种显示器及其制造方法，包括包括包括多个像素的图像显示部分的基板，虚拟测试焊盘和覆盖该虚拟测试焊盘的第一绝缘层。

6. 发明授权

US09252178B2 Pixel of a multi-stacked CMOS image sensor and method of manufacturing the same 有权
标题翻译：多层CMOS图像传感器的像素及其制造方法
公开(公告)号：US09252178B2
公开(公告)日：2016-02-02
申请号：US13205127
申请日：2011-08-08
申请人： Kyung-bae Park , Kyu-sik Kim , Yong-wan Jin , Woong Choi , Kwang-hee Lee , Do-hwan Kim
发明人： Kyung-bae Park , Kyu-sik Kim , Yong-wan Jin , Woong Choi , Kwang-hee Lee , Do-hwan Kim
IPC分类号： H01L31/062 , H01L27/146 , H01L27/30 , H01L27/12 , H01L23/58 , H01L33/08
CPC分类号： H01L27/307 , H01L23/585 , H01L27/1214 , H01L27/14609 , H01L27/14632 , H01L27/14636 , H01L27/14647 , H01L27/14667 , H01L27/14685 , H01L27/14687 , H01L33/08 , H01L2924/0002 , H01L2924/00
摘要： Provided is a pixel of a multi-stacked complementary metal-oxide semiconductor (CMOS) image sensor and a method of manufacturing the image sensor including a light-receiving unit that may include first through third photodiode layers that are sequentially stacked, an integrated circuit (IC) that is formed below the light-receiving unit, electrode layers that are formed on and below each of the first through third photodiode layers, and a contact plug that connects the electrode layer formed below each of the first through third photodiode layers with a transistor of the IC.
摘要翻译：提供了一种多层互补金属氧化物半导体（CMOS）图像传感器的像素，以及包括可以包括依次堆叠的第一至第三光电二极管层的光接收单元的图像传感器的制造方法，集成电路 IC），其形成在所述第一至第三光电二极管层之下和之下形成的电极层，以及将形成在所述第一至第三光电二极管层之下的电极层与所述第一至第三光电二极管层之间形成的电极层的接触插塞晶体管的IC。

7. 发明申请

US20120280340A1 MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
标题翻译：记忆装置及其制造方法
公开(公告)号：US20120280340A1
公开(公告)日：2012-11-08
申请号：US13462472
申请日：2012-05-02
申请人： Sun-kook Kim , Woong Choi , Seung-hoon Han , Yong-wan Jin , Sang-yoon Lee
发明人： Sun-kook Kim , Woong Choi , Seung-hoon Han , Yong-wan Jin , Sang-yoon Lee
IPC分类号： H01L29/82 , H01L21/8246
CPC分类号： B82Y10/00 , B82Y40/00 , G11C11/221 , H01L21/31144 , H01L27/10 , H01L27/101 , H01L27/11507 , H01L27/222 , H01L28/55
摘要： A memory device includes a lower electrode formed on a substrate, and an information storage unit formed on the lower electrode. The information storage unit includes a plurality of information storage layers spaced apart from one another. Each of the plurality of information storage layers is an information unit. A method of manufacturing a memory device uses a porous film to form the plurality of information storage layers.
摘要翻译：存储器件包括形成在衬底上的下电极和形成在下电极上的信息存储单元。信息存储单元包括彼此间隔开的多个信息存储层。多个信息存储层中的每一个是信息单元。存储器件的制造方法使用多孔膜形成多个信息存储层。

8. 发明申请

US20120160750A1 MEMBRANE MODULE AND MEMBRANE MODULE ASSEMBLY, AND IMMERSION-TYPE LAYER-SEPA-RATING APPARATUS INCLUDING SAME 审中-公开
标题翻译：薄膜模块和薄膜模块组件，以及包括其类型的薄膜型隔层评估装置
公开(公告)号：US20120160750A1
公开(公告)日：2012-06-28
申请号：US13375313
申请日：2010-03-23
申请人： Woong Choi , Incheol Kim , Namdoo Kim , Wonseok Lee
发明人： Woong Choi , Incheol Kim , Namdoo Kim , Wonseok Lee
IPC分类号： B01D63/08
CPC分类号： B01D63/082 , B01D63/081 , B01D65/00 , B01D2313/02 , B01D2313/14 , B01D2313/21 , B01D2315/06 , C02F1/44
摘要： Disclosed is a membrane module including: one or more membrane units covering a support and including a membrane having at least one side fused, wherein both sides of each of the membrane units perpendicular to one side of the membrane are molded to be coupled with the first and second frames, respectively.
摘要翻译：公开了一种膜组件，其包括：一个或多个膜单元，其覆盖支撑件并且包括具有至少一个侧面熔合的膜，其中垂直于膜的一侧的每个膜单元的两侧被模制成与第一和第二帧。

9. 发明授权

US07928504B2 Semiconductor memory device and method for manufacturing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07928504B2
公开(公告)日：2011-04-19
申请号：US12494243
申请日：2009-06-29
申请人： Woong Choi
发明人： Woong Choi
IPC分类号： H01L29/788 , H01L29/76 , H01L21/336 , H01L21/3205
CPC分类号： H01L27/10876 , H01L21/823437 , H01L27/1052 , H01L27/10873 , H01L27/10891 , H01L27/10894
摘要： A semiconductor memory device and a method for manufacturing the same are disclosed, which reduce parasitic capacitance generated between a storage node contact and a bit line of a high-integration semiconductor device. A method for manufacturing a semiconductor memory device includes forming a buried word line in an active region of a cell region, forming an insulation layer in the cell region and a lower electrode layer of a gate in a peripheral region so that a height of the insulation layer is substantially equal to that of the lower electrode layer, and providing a first conductive layer over the cell region and the peripheral region to form a bit line layer and an upper electrode layer.
摘要翻译：公开了一种半导体存储器件及其制造方法，其减小了在高集成度半导体器件的存储节点接点和位线之间产生的寄生电容。一种半导体存储器件的制造方法，包括在单元区域的有源区域中形成掩埋字线，在所述单元区域中形成绝缘层，在周边区域形成栅极的下部电极层，使得绝缘体的高度层基本上等于下电极层的层，并且在单元区域和外围区域上提供第一导电层以形成位线层和上电极层。

10. 发明申请

US20100079069A1 DIELECTRIC COMPOSITION AND PLASMA DISPLAY PANEL INCLUDING THE SAME 失效
标题翻译：电介质组合物和等离子体显示面板包括它们
公开(公告)号：US20100079069A1
公开(公告)日：2010-04-01
申请号：US12594421
申请日：2007-12-11
申请人： Woong Choi , Donghee Nam
发明人： Woong Choi , Donghee Nam
IPC分类号： H01J17/49 , C04B35/453
CPC分类号： C03C3/064 , C03C4/16 , C03C8/02 , C03C8/14 , H01J11/12 , H01J11/38
摘要： A dielectric composition for plasma display panel and a plasma display panel including the same are disclosed. The dielectric composition includes about 38 to 68 parts by weight of Bi2O3, about 10 to 35 parts by weight of B2O3, about 1 to 17 parts by weight of SiO2, and about 1 to 15 parts by weight of Al2O3.
摘要翻译：公开了一种用于等离子体显示面板的电介质组合物和包括其的等离子体显示面板。电介质组合物包含约38至68重量份的Bi 2 O 3，约10至35重量份的B 2 O 3，约1至17重量份的SiO 2和约1至15重量份的Al 2 O 3。

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