专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08537633B2 Methods of operating DRAM devices having adjustable internal refresh cycles that vary in response to on-chip temperature changes 有权
标题翻译：操作具有可变内部刷新周期的DRAM器件的方法，其响应片上温度变化而变化
公开(公告)号：US08537633B2
公开(公告)日：2013-09-17
申请号：US13471592
申请日：2012-05-15
申请人： Kwang-Sook Noh , Young-Hun Seo , Jong-Hyun Choi
发明人： Kwang-Sook Noh , Young-Hun Seo , Jong-Hyun Choi
IPC分类号： G11C7/00
CPC分类号： G11C11/402 , G11C11/406 , G11C11/40611 , G11C11/40626 , G11C2211/4061
摘要： An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.
摘要翻译：集成电路存储器件包括刷新控制电路，该刷新控制电路产生具有相对于由存储器件接收的外部存储刷新命令信号的周期而改变的周期的内部存储器刷新命令信号。内部存储器刷新命令的周期中的这种变化可以响应于检测到存储器件的温度变化。特别地，刷新控制电路被配置为使得响应于检测到存储器件的温度降低而使内部存储器刷新命令信号的周期增加。

2. 发明申请

US20120224444A1 METHODS OF OPERATING DRAM DEVICES HAVING ADJUSTABLE INTERNAL REFRESH CYCLES THAT VARY IN RESPONSE TO ON-CHIP TEMPERATURE CHANGES 有权
标题翻译：具有可调节内部温度变化的可调节内部循环的DRAM器件的操作方法
公开(公告)号：US20120224444A1
公开(公告)日：2012-09-06
申请号：US13471592
申请日：2012-05-15
申请人： Kwang-Sook Noh , Young-Hun Seo , Jong-Hyun Choi
发明人： Kwang-Sook Noh , Young-Hun Seo , Jong-Hyun Choi
IPC分类号： G11C7/22
CPC分类号： G11C11/402 , G11C11/406 , G11C11/40611 , G11C11/40626 , G11C2211/4061
摘要： An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.
摘要翻译：集成电路存储器件包括刷新控制电路，该刷新控制电路产生具有相对于由存储器件接收的外部存储刷新命令信号的周期而改变的周期的内部存储器刷新命令信号。内部存储器刷新命令的周期中的这种变化可以响应于检测到存储器件的温度变化。特别地，刷新控制电路被配置为使得响应于检测到存储器件的温度降低而使内部存储器刷新命令信号的周期增加。

3. 发明申请

US20140016424A1 METHODS OF OPERATING DRAM DEVICES HAVING ADJUSTABLE INTERNAL REFRESH CYCLES THAT VARY IN RESPONSE TO ON-CHIP TEMPERATURE CHANGES 有权
标题翻译：具有可调节内部温度变化的可调节内部循环的DRAM器件的操作方法
公开(公告)号：US20140016424A1
公开(公告)日：2014-01-16
申请号：US14017080
申请日：2013-09-03
申请人： Kwang-Sook Noh , Young-Hun Seo , Jong-Hyun Choi
发明人： Kwang-Sook Noh , Young-Hun Seo , Jong-Hyun Choi
IPC分类号： G11C11/402
CPC分类号： G11C11/402 , G11C11/406 , G11C11/40611 , G11C11/40626 , G11C2211/4061
摘要： An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.
摘要翻译：集成电路存储器件包括刷新控制电路，该刷新控制电路产生具有相对于由存储器件接收的外部存储刷新命令信号的周期而改变的周期的内部存储器刷新命令信号。内部存储器刷新命令的周期中的这种变化可以响应于检测到存储器件的温度变化。特别地，刷新控制电路被配置为使得响应于检测到存储器件的温度降低而使内部存储器刷新命令信号的周期增加。

4. 发明授权

US08218137B2 Methods of operating DRAM devices having adjustable internal refresh cycles that vary in response to on-chip temperature changes 有权
标题翻译：操作具有可变内部刷新周期的DRAM器件的方法，其响应片上温度变化而变化
公开(公告)号：US08218137B2
公开(公告)日：2012-07-10
申请号：US12941500
申请日：2010-11-08
申请人： Kwang-Sook Noh , Young-Hun Seo , Jong-Hyun Choi
发明人： Kwang-Sook Noh , Young-Hun Seo , Jong-Hyun Choi
IPC分类号： G11C7/00
CPC分类号： G11C11/402 , G11C11/406 , G11C11/40611 , G11C11/40626 , G11C2211/4061
摘要： An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.
摘要翻译：集成电路存储器件包括刷新控制电路，该刷新控制电路产生具有相对于由存储器件接收的外部存储刷新命令信号的周期而改变的周期的内部存储器刷新命令信号。内部存储器刷新命令的周期中的这种变化可以响应于检测到存储器件的温度变化。特别地，刷新控制电路被配置为使得响应于检测到存储器件的温度降低而使内部存储器刷新命令信号的周期增加。

5. 发明授权

US07843752B2 Circuit and method for controlling refresh periods in semiconductor memory devices 有权
标题翻译：用于控制半导体存储器件中的刷新周期的电路和方法
公开(公告)号：US07843752B2
公开(公告)日：2010-11-30
申请号：US12111468
申请日：2008-04-29
申请人： Kwang-Sook Noh , Young-Hun Seo , Jong-Hyun Choi
发明人： Kwang-Sook Noh , Young-Hun Seo , Jong-Hyun Choi
IPC分类号： G11C7/04
CPC分类号： G11C11/402 , G11C11/406 , G11C11/40611 , G11C11/40626 , G11C2211/4061
摘要： An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.
摘要翻译：集成电路存储器件包括刷新控制电路，该刷新控制电路产生具有相对于由存储器件接收的外部存储刷新命令信号的周期而改变的周期的内部存储器刷新命令信号。内部存储器刷新命令的周期中的这种变化可以响应于检测到存储器件的温度变化。特别地，刷新控制电路被配置为使得响应于检测到存储器件的温度降低而使内部存储器刷新命令信号的周期增加。

6. 发明申请

US20090046531A1 CIRCUIT AND METHOD FOR CONTROLLING REFRESH PERIODS IN SEMICONDUCTOR MEMORY DEVICES 有权
标题翻译：用于控制半导体存储器件中的刷新周期的电路和方法
公开(公告)号：US20090046531A1
公开(公告)日：2009-02-19
申请号：US12111468
申请日：2008-04-29
申请人： Kwang-Sook Noh , Young-Hun Seo , Jong-Hyun Choi
发明人： Kwang-Sook Noh , Young-Hun Seo , Jong-Hyun Choi
IPC分类号： G11C7/04
CPC分类号： G11C11/402 , G11C11/406 , G11C11/40611 , G11C11/40626 , G11C2211/4061
摘要： An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.
摘要翻译：集成电路存储器件包括刷新控制电路，该刷新控制电路产生具有相对于由存储器件接收的外部存储刷新命令信号的周期而改变的周期的内部存储器刷新命令信号。内部存储器刷新命令的周期中的这种变化可以响应于检测到存储器件的温度变化。特别地，刷新控制电路被配置为使得响应于检测到存储器件的温度降低而使内部存储器刷新命令信号的周期增加。

7. 发明申请

US20110116327A1 Memory Devices Having Adjustable Refresh Cycles Responsive to Temperature Changes 有权
标题翻译：具有响应于温度变化的可调节刷新周期的存储器件
公开(公告)号：US20110116327A1
公开(公告)日：2011-05-19
申请号：US12941500
申请日：2010-11-08
申请人： Kwang-Sook Noh , Young-Hun Seo , Jong-Hyun Choi
发明人： Kwang-Sook Noh , Young-Hun Seo , Jong-Hyun Choi
IPC分类号： G11C7/00 , G11C11/402
CPC分类号： G11C11/402 , G11C11/406 , G11C11/40611 , G11C11/40626 , G11C2211/4061
摘要： An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.
摘要翻译：集成电路存储器件包括刷新控制电路，该刷新控制电路产生具有相对于由存储器件接收的外部存储刷新命令信号的周期而改变的周期的内部存储器刷新命令信号。内部存储器刷新命令的周期中的这种变化可以响应于检测到存储器件的温度变化。特别地，刷新控制电路被配置为使得响应于检测到存储器件的温度降低而使内部存储器刷新命令信号的周期增加。

8. 发明申请

US20070263461A1 Methods and devices for preventing data stored in memory from being read out 有权
公开(公告)号：US20070263461A1
公开(公告)日：2007-11-15
申请号：US11826367
申请日：2007-07-13
申请人： Jong-Hyun Choi , Dong-Il Seo , Kyu-Chan Lee , Young-Hun Seo
发明人： Jong-Hyun Choi , Dong-Il Seo , Kyu-Chan Lee , Young-Hun Seo
IPC分类号： G11C7/00
CPC分类号： G11C11/4078 , G11C7/24
摘要： A dynamic random access memory (DRAM) device, including a DRAM core having memory cells for storing data information, and a read protection unit, prevents data stored in the memory cells before power-off, from being read out at power-on.

9. 发明授权

US07515487B2 Internal reference voltage generating circuit for reducing standby current and semiconductor memory device including the same 有权
标题翻译：用于降低待机电流的内部参考电压发生电路和包括其的半导体存储器件
公开(公告)号：US07515487B2
公开(公告)日：2009-04-07
申请号：US11567826
申请日：2006-12-07
申请人： Young-Hun Seo , Dong-Il Seo , Kyu-Chan Lee , Jong-Hyun Choi
发明人： Young-Hun Seo , Dong-Il Seo , Kyu-Chan Lee , Jong-Hyun Choi
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： An internal reference voltage generating circuit that reduces a standby current and the number of pins of a semiconductor memory device, in which a reference voltage is provided to an input buffer that receives a signal through an input to which an on die transmitor resistor is connected, includes: a voltage dividing circuit outputting the reference voltage by a power voltage; a pull down driver connected to an end of the voltage dividing circuit; and a calibration control circuit comparing a voltage level of the input and a voltage level of an end of the voltage dividing circuit, and controlling the on resistor value of the pull down driver according to a result of the comparison. The internal reference voltage generating circuit is operated while the memory controller inputs a signal into a mode register set (MRS) to enable the internal reference voltage generating circuit and the output signal of the MRS is activated.
摘要翻译：一种内部参考电压发生电路，其将待机电流和半导体存储器件的引脚数量减少，其中参考电压被提供给通过连接有管芯发送器电阻器的输入接收信号的输入缓冲器，包括：分压电路，通过电源电压输出基准电压; 连接到分压电路的一端的下拉驱动器; 以及校正控制电路，比较输入的电压电平和分压电路的端部的电压电平，并根据比较的结果来控制下拉驱动器的导通电阻值。内部参考电压产生电路在存储器控制器将信号输入到模式寄存器组（MRS）中的情况下操作，以使能内部基准电压产生电路并且MRS的输出信号被激活。

10. 发明申请

US20050105362A1 Semiconductor memory device for performing refresh operation 有权
标题翻译：用于执行刷新操作的半导体存储器件
公开(公告)号：US20050105362A1
公开(公告)日：2005-05-19
申请号：US10954530
申请日：2004-09-29
申请人： Jong-Hyun Choi , Dong-Il Seo , Young-Hun Seo
发明人： Jong-Hyun Choi , Dong-Il Seo , Young-Hun Seo
IPC分类号： G11C11/401 , G11C11/406 , G11C7/00
CPC分类号： G11C11/40618 , G11C11/406 , G11C11/40622
摘要： A memory device according to the present invention includes multiple refresh modes and a refresh controller. A first refresh mode can respectively select one more memory block among a plurality of banks comprising a plurality of blocks and each of all banks. In addition, the first refresh mode may perform a refresh operation with respect to selected memory blocks. The second refresh mode can select a part of the banks and perform a refresh operation of data with a selected bank. The controller may select one of the first and second refresh modes in a refresh operation.
摘要翻译：根据本发明的存储器件包括多个刷新模式和刷新控制器。第一刷新模式可以分别在包括多个块和所有存储体中的每一个的多个存储体中选择一个存储器块。此外，第一刷新模式可以针对所选择的存储块执行刷新操作。第二刷新模式可以选择一个存储体的一部分并执行与所选存储体的数据的刷新操作。控制器可以在刷新操作中选择第一和第二刷新模式之一。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式