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1. 发明授权

US07541947B2 Semiconductor devices, a system including semiconductor devices and methods thereof 有权
公开(公告)号：US07541947B2
公开(公告)日：2009-06-02
申请号：US11802886
申请日：2007-05-25
申请人： Seung-Jun Bae , Seong-Jin Jang , Kwang-II Park , Woo-Jin Lee
发明人： Seung-Jun Bae , Seong-Jin Jang , Kwang-II Park , Woo-Jin Lee
IPC分类号： H03M7/00
CPC分类号： H03K19/00346 , H04L25/03866 , H04L25/14 , H04L25/4908
摘要： Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

2. 发明申请

US20070206428A1 HIGH-SPEED PHASE-ADJUSTED QUADRATURE DATA RATE (QDR) TRANSCEIVER AND METHOD THEREOF 有权
标题翻译：高速相位调整数据速率（QDR）收发器及其方法
公开(公告)号：US20070206428A1
公开(公告)日：2007-09-06
申请号：US11612800
申请日：2006-12-19
申请人： Seung-Jun Bae , Seong-Jin Jang , Kwang-II Park , Sang-Woong Shin , Ho-Young Song
发明人： Seung-Jun Bae , Seong-Jin Jang , Kwang-II Park , Sang-Woong Shin , Ho-Young Song
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C11/4096
摘要： A high-speed double or quadrature data rate interface semiconductor device and a method thereof are provided. A transmitter (e.g., a data transmitting semiconductor device) for high-speed data transmission transmits a first strobe signal and a second strobe signal, which have a phase difference of 90 degrees there-between, a first group (byte of) data, and a second group (byte of) data. The transmitter adjusts the phase of at least one of the first and second strobe signals based on phase-error information fed back from a receiver and then transmits the phase-adjusted strobe signal to the receiver. The receiver receives the first and second strobe signals from the transmitter and receives the first group (byte of) data and the second group (byte of) data using the first and second strobe signals. The receiver does not require a phase-locked loop (PLL) or a delay-locked loop (DLL), thereby decreasing the circuit area and power consumption of the receiver. In addition, since source synchronization is realized using a strobe signal, phase noise can be efficiently removed.
摘要翻译：提供了一种高速双倍或正交数据速率接口半导体器件及其方法。用于高速数据传输的发射机（例如，数据传输半导体器件）发送第一选通信号和第二选通信号，第一选通信号和第二选通信号之间具有90度的相位差，第一组（字节）数据和第二组（字节）数据。发射机基于从接收机反馈的相位误差信息来调节第一和第二选通信号中的至少一个的相位，然后将相位调整的选通信号发送到接收机。接收机从发送器接收第一和第二选通信号，并使用第一和第二选通信号接收数据的第一组（字节）和第二组（字节）数据。接收机不需要锁相环（PLL）或延迟锁定环（DLL），从而减少接收机的电路面积和功耗。此外，由于使用选通信号实现源同步，因此可以有效地去除相位噪声。

3. 发明申请

US20070290902A1 Semiconductor devices, a system including semiconductor devices and methods thereof 有权
标题翻译：半导体器件，包括半导体器件的系统及其方法
公开(公告)号：US20070290902A1
公开(公告)日：2007-12-20
申请号：US11802886
申请日：2007-05-25
申请人： Seung-Jun Bae , Seong-Jin Jang , Kwang-II Park , Woo-Jin Lee
发明人： Seung-Jun Bae , Seong-Jin Jang , Kwang-II Park , Woo-Jin Lee
IPC分类号： H03M9/00
CPC分类号： H03K19/00346 , H04L25/03866 , H04L25/14 , H04L25/4908
摘要： Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.
摘要翻译：提供半导体器件，包括所述半导体器件的系统及其方法。半导体器件的示例可以接收被调度用于发送的数据，对接收到的数据内的比特数进行加扰，按照给定的伪随机序列排列的加扰顺序。所接收的数据可以是平衡的，使得等于第一逻辑电平的接收数据内的第一比特数与等于第二逻辑电平的接收数据中的第二比特数之间的差异低于阈值。然后可以发送平衡和加扰的接收数据。示例半导体器件可以以任何顺序执行加扰和平衡操作。类似地，在接收端，另一个半导体器件可以通过对发送的数据进行解扰和不平衡来解码原始数据。可以基于发送的数据被加扰和平衡的顺序以顺序执行解扰和不平衡操作。

4. 发明申请

US20070285121A1 Reference voltage generators for reducing and/or eliminating termination mismatch 有权
标题翻译：用于减少和/或消除终止失配的参考电压发生器
公开(公告)号：US20070285121A1
公开(公告)日：2007-12-13
申请号：US11790014
申请日：2007-04-23
申请人： Kwang-II Park , Seung-Jun Bae , Seong-Jin Jang
发明人： Kwang-II Park , Seung-Jun Bae , Seong-Jin Jang
IPC分类号： H03K19/003
CPC分类号： H03K19/017545
摘要： A system including a plurality of transmission lines, a transmitter outputting respective signals to each of the plurality of transmission lines, a receiver receiving each of the plurality of signals via respective transmission lines, the receiver including a connection path connected to a termination voltage, a plurality of termination circuits distributed along the connection path, each termination circuit receiving a unique termination voltage from the connection path, receiving a respective signal and outputting a terminated input signal, a reference voltage generator including multiple reference voltage generator units connected to a common voltage, each reference voltage generator unit uniquely receiving at least one unique termination voltage and outputting a reference voltage, and a plurality of data input buffers receiving respective signals and an appropriate reference voltage of the multiple reference voltages output from the reference voltage generator.
摘要翻译：一种包括多个传输线的系统，向多个传输线中的每一个输出相应信号的发射机，经由各个传输线接收多个信号中的每一个的接收机，所述接收机包括连接到终端电压的连接路径，多个终端电路沿着连接路径分布，每个终端电路从连接路径接收唯一的终端电压，接收相应的信号并输出终止的输入信号;参考电压发生器，包括连接到公共电压的多个参考电压发生器单元，每个参考电压发生器单元独特地接收至少一个唯一的终端电压并输出参考电压，以及多个数据输入缓冲器，其接收相应的信号和从参考电压发生器输出的多个参考电压的适当参考电压。

5. 发明申请

US20090267813A1 Semiconductor devices, a system including semiconductor devices and methods thereof 有权
标题翻译：半导体器件，包括半导体器件的系统及其方法
公开(公告)号：US20090267813A1
公开(公告)日：2009-10-29
申请号：US12453109
申请日：2009-04-29
申请人： Seung-Jun Bae , Seong-Jin Jang , Kwang-Il Park , Woo-Jin Lee
发明人： Seung-Jun Bae , Seong-Jin Jang , Kwang-Il Park , Woo-Jin Lee
IPC分类号： H03M7/00
CPC分类号： H03K19/00346 , H04L25/03866 , H04L25/14 , H04L25/4908
摘要： Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.
摘要翻译：提供半导体器件，包括所述半导体器件的系统及其方法。半导体器件的示例可以接收被调度用于发送的数据，对接收到的数据内的比特顺序进行加扰，按照给定的伪随机序列排列的加扰顺序。所接收的数据可以是平衡的，使得等于第一逻辑电平的接收数据内的第一比特数与等于第二逻辑电平的接收数据中的第二比特数之间的差异低于阈值。然后可以发送平衡和加扰的接收数据。示例半导体器件可以以任何顺序执行加扰和平衡操作。类似地，在接收端，另一个半导体器件可以通过对发送的数据进行解扰和不平衡来解码原始数据。可以基于发送的数据被加扰和平衡的顺序以顺序执行解扰和不平衡操作。

6. 发明申请

US20080278193A1 Reference voltage generators for reducing and/or eliminating termination mismatch 有权
公开(公告)号：US20080278193A1
公开(公告)日：2008-11-13
申请号：US12219213
申请日：2008-07-17
申请人： Kwang-Il Park , Seung-Jun Bae , Seong-Jin Jang
发明人： Kwang-Il Park , Seung-Jun Bae , Seong-Jin Jang
IPC分类号： H03K19/094 , H03K19/0175
CPC分类号： H03K19/017545
摘要： A system including a plurality of transmission lines, a transmitter outputting respective signals to each of the plurality of transmission lines, a receiver receiving each of the plurality of signals via respective transmission lines, the receiver including a connection path connected to a termination voltage, a plurality of termination circuits distributed along the connection path, each termination circuit receiving a unique termination voltage from the connection path, receiving a respective signal and outputting a terminated input signal, a reference voltage generator including multiple reference voltage generator units connected to a common voltage, each reference voltage generator unit uniquely receiving at least one unique termination voltage and outputting a reference voltage, and a plurality of data input buffers receiving respective signals and an appropriate reference voltage of the multiple reference voltages output from the reference voltage generator.

7. 发明申请

US20070229320A1 TRANSMITTING/RECEIVING METHODS AND SYSTEMS FOR DC BALANCE ENCODED DATA INCLUDING SIMULTANEOUS SWITCHING NOISE REDUCING PREAMBLES 有权
标题翻译：用于直流平衡编码数据的发送/接收方法和系统，包括同时开关噪声减少前提
公开(公告)号：US20070229320A1
公开(公告)日：2007-10-04
申请号：US11693264
申请日：2007-03-29
申请人： Seung-Jun Bae , Seong-Jin Jang
发明人： Seung-Jun Bae , Seong-Jin Jang
IPC分类号： H03M7/00
CPC分类号： H03M5/145
摘要： DC balance encoded data is transmitted by transmitting a preamble of dummy data that is configured to provide an intermediate number of bits of a given logic value that is at least one bit of the given logic value but less than a maximum number of bits of the given logic value in the DC balance encoded data, to thereby reduce the simultaneous switching noise that is caused by transmission of a first word of DC balance encoded data. The preamble may contain one or more words of fixed and/or variable dummy data.
摘要翻译：通过发送伪数据的前导码来发送DC平衡编码数据，该伪数据的前导码被配置为提供给定逻辑值的中间位数，该给定逻辑值是给定逻辑值的至少一位，但小于给定逻辑值的最大位数 DC平衡编码数据中的逻辑值，从而减少由DC平衡编码数据的第一字的传输引起的同时开关噪声。前导码可以包含固定和/或可变虚拟数据的一个或多个单词。

8. 发明申请

US20130135956A1 SEMICONDUCTOR DEVICE, A PARALLEL INTERFACE SYSTEM AND METHODS THEREOF 有权
标题翻译：半导体器件，并行接口系统及其方法
公开(公告)号：US20130135956A1
公开(公告)日：2013-05-30
申请号：US13483719
申请日：2012-05-30
申请人： Seung-Jun Bae , Seong-Jin Jang , Beom-Sig Cho
发明人： Seung-Jun Bae , Seong-Jin Jang , Beom-Sig Cho
IPC分类号： G11C7/22
CPC分类号： G11C7/22 , H03K19/0966 , H04L7/0008 , H04L7/033 , H04L7/10
摘要： A memory device includes a clock receiving block, a data transceiver block, a phase detection block, and a phase information transmitter. The clock receiving block is configured to receive a clock signal from a memory controller through a clock signal line and generate a data sampling clock signal and an edge sampling clock signal. The data transceiver block is configured to receive a data signal from the memory controller through a data signal line. The phase detection block is configured to generate phase information in response to the data sampling clock signal, the edge sampling clock signal and the data signal. The phase information transmitter is configured to transmit the phase information to the memory controller through a phase information signal line that is separate from the data signal line.
摘要翻译：存储器件包括时钟接收块，数据收发器块，相位检测块和相位信息发送器。时钟接收块被配置为通过时钟信号线从存储器控制器接收时钟信号，并生成数据采样时钟信号和边沿采样时钟信号。数据收发器模块被配置为通过数据信号线从存储器控制器接收数据信号。相位检测块被配置为响应于数据采样时钟信号，边沿采样时钟信号和数据信号而产生相位信息。相位信息发送器被配置为通过与数据信号线分离的相位信息信号线将相位信息发送到存储器控制器。

9. 发明授权

US07814359B2 High-speed phase-adjusted quadrature data rate (QDR) transceiver and method thereof 有权
标题翻译：高速相位调整正交数据速率（QDR）收发器及其方法
公开(公告)号：US07814359B2
公开(公告)日：2010-10-12
申请号：US11612800
申请日：2006-12-19
申请人： Seung-Jun Bae , Seong-Jin Jang , Kwang-Il Park , Sang-Woong Shin , Ho-Young Song
发明人： Seung-Jun Bae , Seong-Jin Jang , Kwang-Il Park , Sang-Woong Shin , Ho-Young Song
IPC分类号： G06F12/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C11/4096
摘要： A high-speed double or quadrature data rate interface semiconductor device and a method thereof are provided. A transmitter (e.g., a data transmitting semiconductor device) for high-speed data transmission transmits a first strobe signal and a second strobe signal, which have a phase difference of 90 degrees there-between, a first group (byte of) data, and a second group (byte of) data. The transmitter adjusts the phase of at least one of the first and second strobe signals based on phase-error information fed back from a receiver and then transmits the phase-adjusted strobe signal to the receiver. The receiver receives the first and second strobe signals from the transmitter and receives the first group (byte of) data and the second group (byte of) data using the first and second strobe signals. The receiver does not require a phase-locked loop (PLL) or a delay-locked loop (DLL), thereby decreasing the circuit area and power consumption of the receiver. In addition, since source synchronization is realized using a strobe signal, phase noise can be efficiently removed.
摘要翻译：提供了一种高速双倍或正交数据速率接口半导体器件及其方法。用于高速数据传输的发射机（例如，数据传输半导体器件）发射第一选通信号和第二选通信号，第一选通信号和第二选通信号之间具有90度的相位差，第一组（字节）数据和第二组（字节）数据。发射机基于从接收机反馈的相位误差信息来调节第一和第二选通信号中的至少一个的相位，然后将相位调整的选通信号发送到接收机。接收机从发送器接收第一和第二选通信号，并使用第一和第二选通信号接收数据的第一组（字节）和第二组（字节）数据。接收机不需要锁相环（PLL）或延迟锁定环（DLL），从而减少接收机的电路面积和功耗。此外，由于使用选通信号实现源同步，因此可以有效地去除相位噪声。

10. 发明申请

US20090225622A1 CIRCUIT AND METHODS FOR ELIMINATING SKEW BETWEEN SIGNALS IN SEMICODUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：用于消除半导体集成电路中信号之间的差异的电路和方法
公开(公告)号：US20090225622A1
公开(公告)日：2009-09-10
申请号：US12430163
申请日：2009-04-27
申请人： Seung-Jun Bae , Kwang-Il Park , Seong-Jin Jang
发明人： Seung-Jun Bae , Kwang-Il Park , Seong-Jin Jang
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C5/063 , G11C7/02 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/222
摘要： A circuit for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device and a memory controller includes an edge information storage unit which stores edge information output from the semiconductor memory device, a pseudo data pattern generating unit which outputs pseudo data including a pattern similar to actually transmitted data, a phase detecting unit which receives the edge information from the edge information storage unit and the pseudo data from the pseudo data pattern generating unit to detect a phase difference between the data and the clock signal and generate a corresponding detection result, and a phase control unit which controls a phase of the clock signal according to the corresponding detection result from the phase detecting unit, so as to eliminate a per-data input/output pin skew in a data write and read operation of the semiconductor memory device.
摘要翻译：一种用于消除半导体存储器件和存储器控制器之间的接口中的数据与时钟信号之间的偏斜的电路，包括存储从半导体存储器件输出的边沿信息的边缘信息存储单元，伪数据模式生成单元，其输出伪数据，包括与实际发送的数据类似的模式;相位检测单元，其从边缘信息存储单元接收边缘信息，并从伪数据模式产生单元接收伪数据，以检测数据和时钟信号之间的相位差，并产生相应的检测结果，以及相位控制单元，其根据来自相位检测单元的相应检测结果控制时钟信号的相位，以便消除数据写入和读取操作中的每数据输入/输出引脚偏移的半导体存储器件。

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