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1. 发明申请

US20060223296A1 Semiconductor device having self-aligned silicide layer and method thereof 审中-公开
标题翻译：具有自对准硅化物层的半导体器件及其方法
公开(公告)号：US20060223296A1
公开(公告)日：2006-10-05
申请号：US11180885
申请日：2005-07-13
申请人： Min-Chul Sun , Ja-Hum Ku , Sug-Woo Jung , Sung-Kee Han , Min-Joo Kim , Kwan-Jong Roh
发明人： Min-Chul Sun , Ja-Hum Ku , Sug-Woo Jung , Sung-Kee Han , Min-Joo Kim , Kwan-Jong Roh
IPC分类号： H01L21/3205 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/28518 , H01L29/665
摘要： A semiconductor device having a self-aligned silicide layer and a method thereof are provided. The device includes a device isolation layer formed on the substrate to define an active region and a gate pattern crossing over the active region. A spacer insulating layer is formed on both sidewalls of the gate pattern. First and second salicide layers are formed on an upper portion of the gate pattern, and the first salicide layer is formed on the active region between the spacer insulating layer and the device isolation layer. The first and the second salicide layers on the gate pattern are alternately formed to be connected with each other. The first salicide layer is agglomeratedly formed on a narrow gate pattern, and the second salicide layer is formed within interrupted portions of the first salicide layer, thereby forming a patched salicide layer.
摘要翻译：提供了具有自对准硅化物层的半导体器件及其方法。该器件包括在衬底上形成的器件隔离层，以限定有源区和跨越有源区的栅极图案。在栅极图案的两个侧壁上形成间隔绝缘层。第一和第二自对准硅化物层形成在栅极图案的上部，并且第一自对准硅化物层形成在间隔绝缘层和器件隔离层之间的有源区上。栅极图案上的第一和第二自对准硅化物层交替地形成为彼此连接。第一自对准硅化物层在窄栅极图案上聚集形成，并且第二自对准硅化物层形成在第一自对准硅化物层的中断部分内，从而形成修补的自对准硅化物层。

2. 发明申请

US20060003534A1 Salicide process using bi-metal layer and method of fabricating semiconductor device using the same 审中-公开
标题翻译：使用双金属层的硅化物工艺及使用其制造半导体器件的方法
公开(公告)号：US20060003534A1
公开(公告)日：2006-01-05
申请号：US11147633
申请日：2005-06-08
申请人： Kwan-Jong Roh , Min-Chul Sun , Ja-Hum Ku , Sug-Woo Jung , Min-Joo Kim , Sung-Kee Han
发明人： Kwan-Jong Roh , Min-Chul Sun , Ja-Hum Ku , Sug-Woo Jung , Min-Joo Kim , Sung-Kee Han
IPC分类号： H01L21/336
CPC分类号： H01L21/28052 , H01L21/28518 , H01L29/4933 , H01L29/665 , H01L29/66545
摘要： A salicide process using a bi-metal layer and method of fabricating a semiconductor substrate using the same are disclosed herein. The salicide process includes forming a main metal layer on a semiconductor substrate containing silicon. A main metal alloy layer containing at least one species of alloy element is formed on the main metal layer. The semiconductor substrate having the main metal layer and the main metal alloy layer is annealed to form a main metal alloy silicide layer. According to an exemplary embodiment of the present invention, the main metal layer may be formed of a nickel (Ni) layer, and the main metal alloy layer may be formed of a nickel tantalum alloy layer. In this case, a nickel tantalum silicide layer having improved thermal stability and electrical characteristics are formed.
摘要翻译：本文公开了使用双金属层的自对准硅化物工艺和使用其制造半导体衬底的方法。自对准硅化物工艺包括在含硅的半导体衬底上形成主金属层。在主金属层上形成含有至少一种合金元素的主金属合金层。将具有主金属层和主金属合金层的半导体基板退火以形成主金属合金硅化物层。根据本发明的示例性实施例，主金属层可以由镍（Ni）层形成，并且主金属合金层可以由镍钽合金层形成。在这种情况下，形成具有改善的热稳定性和电特性的镍硅化钽层。

3. 发明授权

US07232756B2 Nickel salicide process with reduced dopant deactivation 有权
标题翻译：具有减少掺杂剂钝化的镍硅化物工艺
公开(公告)号：US07232756B2
公开(公告)日：2007-06-19
申请号：US10812003
申请日：2004-03-30
申请人： Ja-Hum Ku , Kwan-Jong Roh , Min-Chul Sun , Min-Joo Kim , Sug-Woo Jung , Sun-Pil Youn
发明人： Ja-Hum Ku , Kwan-Jong Roh , Min-Chul Sun , Min-Joo Kim , Sug-Woo Jung , Sun-Pil Youn
IPC分类号： H01L21/44
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28061 , H01L21/28518 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： Provided are exemplary methods for forming a semiconductor devices incorporating silicide layers formed at temperatures below about 700° C., such as nickel silicides, that are formed after completion of a silicide blocking layer (SBL). The formation of the SBL tends to deactivate dopant species in the gate, lightly-doped drain and/or source/drain regions. The exemplary methods include a post-SBL activation anneal either in place of or in addition to the traditional post-implant activation anneal. The use of the post-SBL anneal produces CMOS transistors having properties that reflect reactivation of sufficient dopant to overcome the SBL process effects, while allowing the use of lower temperature silicides, including nickel silicides and, in particular, nickel silicides incorporating a minor portion of an alloying metal, such as tantalum, the exhibits reduced agglomeration and improved temperature stability.
摘要翻译：提供了形成在硅化物阻挡层（SBL）完成之后形成的在低于约700℃的温度下形成的硅化物层的半导体器件（例如硅化镍）的示例性方法。 SBL的形成倾向于使栅极，轻掺杂漏极和/或源极/漏极区域中的掺杂物质失活。示例性方法包括后SBL激活退火，代替传统的植入物后激活退火或替代传统的植入后激活退火。后SBL退火的使用产生具有反映充分掺杂剂的再活化以克服SBL工艺效应的性质的CMOS晶体管，同时允许使用较低温度的硅化物，包括硅化镍，特别是掺入较小部分的硅化镍合金金属如钽，表现出减少的团聚和改善的温度稳定性。

4. 发明授权

US07084061B2 Methods of fabricating a semiconductor device having MOS transistor with strained channel 有权
标题翻译：制造具有应变通道的MOS晶体管的半导体器件的方法
公开(公告)号：US07084061B2
公开(公告)日：2006-08-01
申请号：US10799788
申请日：2004-03-12
申请人： Min-Chul Sun , Ja-Hum Ku , Sug-Woo Jung , Sun-Pil Youn , Min-Joo Kim , Kwan-Jong Roh
发明人： Min-Chul Sun , Ja-Hum Ku , Sug-Woo Jung , Sun-Pil Youn , Min-Joo Kim , Kwan-Jong Roh
IPC分类号： H01L21/44
CPC分类号： H01L29/7843 , H01L21/324 , H01L21/823807 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： Methods of fabricating a semiconductor device having a MOS transistor with a strained channel are provided. The method includes forming a MOS transistor at a portion of a semiconductor substrate. The MOS transistor is formed to have source/drain regions spaced apart from each other and a gate electrode located over a channel region between the source/drain regions. A stress layer is formed on the semiconductor substrate having the MOS transistor. The stress layer is then annealed to convert a physical stress of the stress layer into a tensile stress or increase a tensile stress of the stress layer.
摘要翻译：提供了制造具有具有应变通道的MOS晶体管的半导体器件的方法。该方法包括在半导体衬底的一部分处形成MOS晶体管。 MOS晶体管形成为具有彼此间隔开的源极/漏极区域和位于源极/漏极区域之间的沟道区域上方的栅极电极。在具有MOS晶体管的半导体衬底上形成应力层。然后应力层退火以将应力层的物理应力转变为拉伸应力或增加应力层的拉伸应力。

5. 发明授权

US07569483B2 Methods of forming metal silicide layers by annealing metal layers using inert heat transferring gases established in a convection apparatus 有权
标题翻译：通过在对流装置中建立的惰性热传递气体退火金属层来形成金属硅化物层的方法
公开(公告)号：US07569483B2
公开(公告)日：2009-08-04
申请号：US11199439
申请日：2005-08-08
申请人： Sug-Woo Jung , Gil-Heyun Choi , Jong-Ho Yun , Kwan-Jong Roh , Eun-Ji Jung , Hyun-Su Kim
发明人： Sug-Woo Jung , Gil-Heyun Choi , Jong-Ho Yun , Kwan-Jong Roh , Eun-Ji Jung , Hyun-Su Kim
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： Methods of forming metal silicide layers include a convection-based annealing step to convert a metal layer into a metal silicide layer. These methods may include forming a silicon layer on a substrate and forming a metal layer (e.g., nickel layer) in direct contact with the silicon layer. A step is then performed to convert at least a portion of the metal layer into a metal silicide layer. This conversion step is includes exposing the metal layer to an inert heat transferring gas (e.g., argon, nitrogen) in a convection or conduction apparatus.
摘要翻译：形成金属硅化物层的方法包括将金属层转化为金属硅化物层的基于对流的退火步骤。这些方法可以包括在衬底上形成硅层并形成与硅层直接接触的金属层（例如，镍层）。然后执行步骤以将至少一部分金属层转化为金属硅化物层。该转化步骤包括在对流或传导装置中将金属层暴露于惰性传热气体（例如氩气，氮气）。

6. 发明申请

US20060063380A1 Salicide process and method of fabricating semiconductor device using the same 有权
标题翻译：硅化物工艺及其制造使用其的半导体器件的方法
公开(公告)号：US20060063380A1
公开(公告)日：2006-03-23
申请号：US11199439
申请日：2005-08-08
申请人： Sug-Woo Jung , Gil-Heyun Choi , Jong-Ho Yun , Kwan-Jong Roh , Eun-Ji Jung , Hyun-Su Kim
发明人： Sug-Woo Jung , Gil-Heyun Choi , Jong-Ho Yun , Kwan-Jong Roh , Eun-Ji Jung , Hyun-Su Kim
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： Methods of forming metal silicide layers include a convection-based annealing step to convert a metal layer into a metal silicide layer. These methods may include forming a silicon layer on a substrate and forming a metal layer (e.g., nickel layer) in direct contact with the silicon layer. A step is then performed to convert at least a portion of the metal layer into a metal silicide layer. This conversion step is includes exposing the metal layer to an inert heat transferring gas (e.g., argon, nitrogen) in a convection or conduction apparatus.
摘要翻译：形成金属硅化物层的方法包括将金属层转化为金属硅化物层的基于对流的退火步骤。这些方法可以包括在衬底上形成硅层并形成与硅层直接接触的金属层（例如，镍层）。然后执行步骤以将至少一部分金属层转化为金属硅化物层。该转化步骤包括在对流或传导装置中将金属层暴露于惰性传热气体（例如氩气，氮气）。

7. 发明申请

US20120149166A1 METHOD OF FORMING TITANIUM NITRADE (TiN) FILM, NONVOLATILE MEMORY DEVICE USING THE TiN FILM, AND METHOD OF MANUFACTURING THE NONVOLATILE MEMORY DEVICE 审中-公开
标题翻译：使用TiN膜形成钛铁（TiN）膜，非易失存储器件的方法和制造非易失性存储器件的方法
公开(公告)号：US20120149166A1
公开(公告)日：2012-06-14
申请号：US13301047
申请日：2011-11-21
申请人： Young-Lim PARK , Jin-Il Lee , Kyung-Min Chung , Sug-Woo Jung , Chang-Su Kim
发明人： Young-Lim PARK , Jin-Il Lee , Kyung-Min Chung , Sug-Woo Jung , Chang-Su Kim
IPC分类号： H01L21/20 , H01L21/768
CPC分类号： C23C16/34 , C23C16/45529 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/16
摘要： A method of manufacturing a nonvolatile memory device includes forming an insulating film pattern, which includes apertures, on a substrate, forming a switching element in each of the apertures, forming a bottom electrode on the switching element by using a silicon (Si)-doped titanium nitride (TiN) film, and forming a variable resistance material pattern on the bottom electrode. The Si-doped TiN film is formed by repeatedly forming a TiN film and doping the TiN film with Si.
摘要翻译：一种制造非易失性存储器件的方法包括：在衬底上形成包括孔的绝缘膜图案，在每个孔中形成开关元件，通过使用硅（Si）掺杂在开关元件上形成底电极氮化钛（TiN）膜，并且在底部电极上形成可变电阻材料图案。通过重复形成TiN膜并用Si掺杂TiN膜来形成Si掺杂的TiN膜。

8. 发明申请

US20120119181A1 SEMICONDUCTOR DEVICE INCLUDING BUFFER ELECTRODE, METHOD OF FABRICATING THE SAME, AND MEMORY SYSTEM INCLUDING THE SAME 有权
标题翻译：包括缓冲电极的半导体器件，其制造方法以及包括其的存储器系统
公开(公告)号：US20120119181A1
公开(公告)日：2012-05-17
申请号：US13241506
申请日：2011-09-23
申请人： Gyu-Hwan OH , Shin-Jae Kang , Sug-Woo Jung , Dong-Hyun Im , Chan-Mi Lee
发明人： Gyu-Hwan OH , Shin-Jae Kang , Sug-Woo Jung , Dong-Hyun Im , Chan-Mi Lee
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L27/224 , H01L27/2409 , H01L27/2472 , H01L45/04 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/146
摘要： A semiconductor device includes a switching device disposed on a substrate. A buffer electrode pattern is disposed on the switching device. The buffer electrode pattern includes a first region having a first vertical thickness, and a second region having a second vertical thickness smaller than the first vertical thickness. A lower electrode pattern is disposed on the first region of the buffer electrode pattern. A trim insulating pattern is disposed on the second region of the buffer electrode pattern. A variable resistive pattern is disposed on the lower electrode pattern.
摘要翻译：半导体器件包括设置在基板上的开关器件。缓冲电极图案设置在开关装置上。缓冲电极图案包括具有第一垂直厚度的第一区域和具有小于第一垂直厚度的第二垂直厚度的第二区域。下部电极图案设置在缓冲电极图案的第一区域上。修整绝缘图案设置在缓冲电极图案的第二区域上。可变电阻图案设置在下电极图案上。

9. 发明申请

US20080199991A1 STACKED SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION 有权
标题翻译：堆叠半导体器件和制造方法
公开(公告)号：US20080199991A1
公开(公告)日：2008-08-21
申请号：US12108591
申请日：2008-04-24
申请人： Hyun-Su Kim , Gil-Heyun Choi , Jong-Ho Yun , Sug-Woo Jung , Eun-Ji Jung
发明人： Hyun-Su Kim , Gil-Heyun Choi , Jong-Ho Yun , Sug-Woo Jung , Eun-Ji Jung
IPC分类号： H01L21/84
CPC分类号： H01L27/0688 , H01L21/8221
摘要： A stacked semiconductor device comprises a lower transistor formed on a semiconductor substrate, a lower interlevel insulation film formed on the semiconductor substrate over the lower transistor, an upper transistor formed on the lower interlayer insulation film over the lower transistor, and an upper interlevel insulation film formed on the lower interlevel insulation film over the upper transistor. The stacked semiconductor device further comprises a contact plug connected between a drain or source region of the lower transistor and a source or drain region of the upper transistor, and an extension layer connected to a lateral face of the source or drain region of the upper transistor to enlarge an area of contact between the source or drain region of the upper transistor and a side of the contact plug.
摘要翻译：叠层半导体器件包括形成在半导体衬底上的下晶体管，形成在半导体衬底上的下层晶体管上的下层间绝缘膜，形成在下晶体管上的下层间绝缘膜上的上晶体管，以及上层间绝缘膜形成在上层晶体管上的较低层间绝缘膜上。叠层半导体器件还包括连接在下晶体管的漏极或源极区域与上部晶体管的源极或漏极区域之间的接触插塞以及连接到上部晶体管的源极或漏极区域的侧面的延伸层以扩大上部晶体管的源极或漏极区域与接触插塞的一侧之间的接触面积。

10. 发明授权

US08841643B2 Semiconductor memory device including buffer electrode 有权
标题翻译：半导体存储器件包括缓冲电极
公开(公告)号：US08841643B2
公开(公告)日：2014-09-23
申请号：US13241506
申请日：2011-09-23
申请人： Gyu-Hwan Oh , Shin-Jae Kang , Sug-Woo Jung , Dong-Hyun Im , Chan-Mi Lee
发明人： Gyu-Hwan Oh , Shin-Jae Kang , Sug-Woo Jung , Dong-Hyun Im , Chan-Mi Lee
IPC分类号： H01L45/00 , H01L27/24 , H01L27/22
CPC分类号： H01L45/06 , H01L27/224 , H01L27/2409 , H01L27/2472 , H01L45/04 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/146
摘要： A semiconductor device includes a switching device disposed on a substrate. A buffer electrode pattern is disposed on the switching device. The buffer electrode pattern includes a first region having a first vertical thickness, and a second region having a second vertical thickness smaller than the first vertical thickness. A lower electrode pattern is disposed on the first region of the buffer electrode pattern. A trim insulating pattern is disposed on the second region of the buffer electrode pattern. A variable resistive pattern is disposed on the lower electrode pattern.
摘要翻译：半导体器件包括设置在基板上的开关器件。缓冲电极图案设置在开关装置上。缓冲电极图案包括具有第一垂直厚度的第一区域和具有小于第一垂直厚度的第二垂直厚度的第二区域。下部电极图案设置在缓冲电极图案的第一区域上。修整绝缘图案设置在缓冲电极图案的第二区域上。可变电阻图案设置在下电极图案上。

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