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1. 发明申请

US20060003534A1 Salicide process using bi-metal layer and method of fabricating semiconductor device using the same 审中-公开
标题翻译：使用双金属层的硅化物工艺及使用其制造半导体器件的方法
公开(公告)号：US20060003534A1
公开(公告)日：2006-01-05
申请号：US11147633
申请日：2005-06-08
申请人： Kwan-Jong Roh , Min-Chul Sun , Ja-Hum Ku , Sug-Woo Jung , Min-Joo Kim , Sung-Kee Han
发明人： Kwan-Jong Roh , Min-Chul Sun , Ja-Hum Ku , Sug-Woo Jung , Min-Joo Kim , Sung-Kee Han
IPC分类号： H01L21/336
CPC分类号： H01L21/28052 , H01L21/28518 , H01L29/4933 , H01L29/665 , H01L29/66545
摘要： A salicide process using a bi-metal layer and method of fabricating a semiconductor substrate using the same are disclosed herein. The salicide process includes forming a main metal layer on a semiconductor substrate containing silicon. A main metal alloy layer containing at least one species of alloy element is formed on the main metal layer. The semiconductor substrate having the main metal layer and the main metal alloy layer is annealed to form a main metal alloy silicide layer. According to an exemplary embodiment of the present invention, the main metal layer may be formed of a nickel (Ni) layer, and the main metal alloy layer may be formed of a nickel tantalum alloy layer. In this case, a nickel tantalum silicide layer having improved thermal stability and electrical characteristics are formed.
摘要翻译：本文公开了使用双金属层的自对准硅化物工艺和使用其制造半导体衬底的方法。自对准硅化物工艺包括在含硅的半导体衬底上形成主金属层。在主金属层上形成含有至少一种合金元素的主金属合金层。将具有主金属层和主金属合金层的半导体基板退火以形成主金属合金硅化物层。根据本发明的示例性实施例，主金属层可以由镍（Ni）层形成，并且主金属合金层可以由镍钽合金层形成。在这种情况下，形成具有改善的热稳定性和电特性的镍硅化钽层。

2. 发明申请

US20060223296A1 Semiconductor device having self-aligned silicide layer and method thereof 审中-公开
标题翻译：具有自对准硅化物层的半导体器件及其方法
公开(公告)号：US20060223296A1
公开(公告)日：2006-10-05
申请号：US11180885
申请日：2005-07-13
申请人： Min-Chul Sun , Ja-Hum Ku , Sug-Woo Jung , Sung-Kee Han , Min-Joo Kim , Kwan-Jong Roh
发明人： Min-Chul Sun , Ja-Hum Ku , Sug-Woo Jung , Sung-Kee Han , Min-Joo Kim , Kwan-Jong Roh
IPC分类号： H01L21/3205 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/28518 , H01L29/665
摘要： A semiconductor device having a self-aligned silicide layer and a method thereof are provided. The device includes a device isolation layer formed on the substrate to define an active region and a gate pattern crossing over the active region. A spacer insulating layer is formed on both sidewalls of the gate pattern. First and second salicide layers are formed on an upper portion of the gate pattern, and the first salicide layer is formed on the active region between the spacer insulating layer and the device isolation layer. The first and the second salicide layers on the gate pattern are alternately formed to be connected with each other. The first salicide layer is agglomeratedly formed on a narrow gate pattern, and the second salicide layer is formed within interrupted portions of the first salicide layer, thereby forming a patched salicide layer.
摘要翻译：提供了具有自对准硅化物层的半导体器件及其方法。该器件包括在衬底上形成的器件隔离层，以限定有源区和跨越有源区的栅极图案。在栅极图案的两个侧壁上形成间隔绝缘层。第一和第二自对准硅化物层形成在栅极图案的上部，并且第一自对准硅化物层形成在间隔绝缘层和器件隔离层之间的有源区上。栅极图案上的第一和第二自对准硅化物层交替地形成为彼此连接。第一自对准硅化物层在窄栅极图案上聚集形成，并且第二自对准硅化物层形成在第一自对准硅化物层的中断部分内，从而形成修补的自对准硅化物层。

3. 发明授权

US07232756B2 Nickel salicide process with reduced dopant deactivation 有权
标题翻译：具有减少掺杂剂钝化的镍硅化物工艺
公开(公告)号：US07232756B2
公开(公告)日：2007-06-19
申请号：US10812003
申请日：2004-03-30
申请人： Ja-Hum Ku , Kwan-Jong Roh , Min-Chul Sun , Min-Joo Kim , Sug-Woo Jung , Sun-Pil Youn
发明人： Ja-Hum Ku , Kwan-Jong Roh , Min-Chul Sun , Min-Joo Kim , Sug-Woo Jung , Sun-Pil Youn
IPC分类号： H01L21/44
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28061 , H01L21/28518 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： Provided are exemplary methods for forming a semiconductor devices incorporating silicide layers formed at temperatures below about 700° C., such as nickel silicides, that are formed after completion of a silicide blocking layer (SBL). The formation of the SBL tends to deactivate dopant species in the gate, lightly-doped drain and/or source/drain regions. The exemplary methods include a post-SBL activation anneal either in place of or in addition to the traditional post-implant activation anneal. The use of the post-SBL anneal produces CMOS transistors having properties that reflect reactivation of sufficient dopant to overcome the SBL process effects, while allowing the use of lower temperature silicides, including nickel silicides and, in particular, nickel silicides incorporating a minor portion of an alloying metal, such as tantalum, the exhibits reduced agglomeration and improved temperature stability.
摘要翻译：提供了形成在硅化物阻挡层（SBL）完成之后形成的在低于约700℃的温度下形成的硅化物层的半导体器件（例如硅化镍）的示例性方法。 SBL的形成倾向于使栅极，轻掺杂漏极和/或源极/漏极区域中的掺杂物质失活。示例性方法包括后SBL激活退火，代替传统的植入物后激活退火或替代传统的植入后激活退火。后SBL退火的使用产生具有反映充分掺杂剂的再活化以克服SBL工艺效应的性质的CMOS晶体管，同时允许使用较低温度的硅化物，包括硅化镍，特别是掺入较小部分的硅化镍合金金属如钽，表现出减少的团聚和改善的温度稳定性。

4. 发明授权

US07084061B2 Methods of fabricating a semiconductor device having MOS transistor with strained channel 有权
标题翻译：制造具有应变通道的MOS晶体管的半导体器件的方法
公开(公告)号：US07084061B2
公开(公告)日：2006-08-01
申请号：US10799788
申请日：2004-03-12
申请人： Min-Chul Sun , Ja-Hum Ku , Sug-Woo Jung , Sun-Pil Youn , Min-Joo Kim , Kwan-Jong Roh
发明人： Min-Chul Sun , Ja-Hum Ku , Sug-Woo Jung , Sun-Pil Youn , Min-Joo Kim , Kwan-Jong Roh
IPC分类号： H01L21/44
CPC分类号： H01L29/7843 , H01L21/324 , H01L21/823807 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： Methods of fabricating a semiconductor device having a MOS transistor with a strained channel are provided. The method includes forming a MOS transistor at a portion of a semiconductor substrate. The MOS transistor is formed to have source/drain regions spaced apart from each other and a gate electrode located over a channel region between the source/drain regions. A stress layer is formed on the semiconductor substrate having the MOS transistor. The stress layer is then annealed to convert a physical stress of the stress layer into a tensile stress or increase a tensile stress of the stress layer.
摘要翻译：提供了制造具有具有应变通道的MOS晶体管的半导体器件的方法。该方法包括在半导体衬底的一部分处形成MOS晶体管。 MOS晶体管形成为具有彼此间隔开的源极/漏极区域和位于源极/漏极区域之间的沟道区域上方的栅极电极。在具有MOS晶体管的半导体衬底上形成应力层。然后应力层退火以将应力层的物理应力转变为拉伸应力或增加应力层的拉伸应力。

5. 发明申请

US20050236715A1 Nickel alloy salicide transistor structure and method for manufacturing same 审中-公开
标题翻译：镍合金硅化物晶体管结构及其制造方法
公开(公告)号：US20050236715A1
公开(公告)日：2005-10-27
申请号：US11148301
申请日：2005-06-09
申请人： Ja-Hum Ku , Kwan-Jong Roh , Min-Chul Sun , Min-Joo Kim
发明人： Ja-Hum Ku , Kwan-Jong Roh , Min-Chul Sun , Min-Joo Kim
IPC分类号： H01L21/28 , H01L21/20 , H01L21/24 , H01L21/285 , H01L21/3205 , H01L21/336 , H01L23/52 , H01L29/40 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28061 , H01L21/28518 , H01L29/4941 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： Provided are exemplary methods for forming a nickel silicide layer and semiconductor devices incorporating a nickel silicide layer that provides increased stability for subsequent processing at temperatures above 450° C. In particular, the nickel silicide layer is formed from a nickel alloy having a minor portion of an alloying metal, such as tantalum, and exhibits reduced agglomeration and retarded the phase transition between NiSi and NiSi2 to suppress increases in the sheet resistance and improve the utility for use with fine patterns. As formed, the nickel silicide layer includes both a lower layer consisting primarily of nickel and silicon and a thinner upper layer that incorporates the majority of the alloying metal.
摘要翻译：提供了用于形成硅化镍层的示例性方法和结合有硅化镍层的半导体器件，其为在450℃以上的温度下进行后续处理提供了更高的稳定性。特别地，硅化镍层由具有少部分合金化金属如钽，并且表现出减少的附聚并延缓NiSi和NiSi 2 N之间的相变，以抑制薄层电阻的增加并提高使用精细图案的效用。如所形成的那样，硅化镍层包括主要由镍和硅组成的下层和掺入大部分合金金属的较薄的上层。

6. 发明授权

US07781322B2 Nickel alloy salicide transistor structure and method for manufacturing same 有权
标题翻译：镍合金硅化物晶体管结构及其制造方法
公开(公告)号：US07781322B2
公开(公告)日：2010-08-24
申请号：US10726638
申请日：2003-12-04
申请人： Ja-Hum Ku , Kwan-Jong Roh , Min-Chul Sun , Min-Joo Kim
发明人： Ja-Hum Ku , Kwan-Jong Roh , Min-Chul Sun , Min-Joo Kim
IPC分类号： H01L21/3205
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28061 , H01L21/28518 , H01L29/4941 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： Provided are exemplary methods for forming a nickel silicide layer and semiconductor devices incorporating a nickel silicide layer that provides increased stability for subsequent processing at temperatures above 450° C. In particular, the nickel silicide layer is formed from a nickel alloy having a minor portion of an alloying metal, such as tantalum, and exhibits reduced agglomeration and retarded the phase transition between NiSi and NiSi2 to suppress increases in the sheet resistance and improve the utility for use with fine patterns. As formed, the nickel silicide layer includes both a lower layer consisting primarily of nickel and silicon and a thinner upper layer that incorporates the majority of the alloying metal.
摘要翻译：提供了用于形成硅化镍层的示例性方法和结合有硅化镍层的半导体器件，其为在450℃以上的温度下进行后续处理提供了更高的稳定性。特别地，硅化镍层由具有少部分合金化金属如钽，并且显示减少的结块并延缓NiSi和NiSi2之间的相变，以抑制薄层电阻的增加并提高使用精细图案的效用。如所形成的那样，硅化镍层包括主要由镍和硅组成的下层和掺入大部分合金金属的较薄的上层。

7. 发明申请

US20050158996A1 Nickel salicide processes and methods of fabricating semiconductor devices using the same 审中-公开
标题翻译：镍硅化物工艺及使用其制造半导体器件的方法
公开(公告)号：US20050158996A1
公开(公告)日：2005-07-21
申请号：US10988848
申请日：2004-11-16
申请人： Min-Joo Kim , Ja-Hum Ku , Min-Chul Sun , Kwan-Jong Roh
发明人： Min-Joo Kim , Ja-Hum Ku , Min-Chul Sun , Kwan-Jong Roh
IPC分类号： H01L21/24 , H01L21/28 , H01L21/285 , H01L21/336 , H01L29/78 , H01L21/322
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28518
摘要： A nickel salicide process includes preparing a substrate having a silicon region and an insulating region containing silicon. Nickel is deposited on the substrate, and the nickel is annealed at a first temperature of 300° C. to 380° C. to selectively form a mono-nickel mono-silicide layer on the silicon region and to leave an unreacted nickel layer on the insulating region. The unreacted nickel layer is selectively removed to expose the insulating region and to leave the mono-nickel mono-silicide layer on the silicon region. Subsequently, the mono-nickel mono-silicide layer is annealed at a second temperature which is higher than the first temperature to form a thermally stable mono-nickel mono-silicide layer and without a phase transition of the mono-nickel mono-silicide layer.
摘要翻译：镍硅化物工艺包括制备具有硅区和含硅绝缘区的衬底。镍沉积在衬底上，并且镍在300℃至380℃的第一温度下退火，以在硅区域上选择性地形成单镍单硅化物层，并在其上留下未反应的镍层绝缘区域。选择性地去除未反应的镍层以暴露绝缘区域并且在硅区域上留下单镍单硅化物层。随后，在高于第一温度的第二温度下对单镍单硅化物层进行退火，以形成热稳定的单镍一硅化物层，并且不存在单镍一硅化物层的相变。

8. 发明申请

US20070034966A1 Dual gate CMOS semiconductor devices and methods of fabricating such devices 审中-公开
标题翻译：双栅极CMOS半导体器件及其制造方法
公开(公告)号：US20070034966A1
公开(公告)日：2007-02-15
申请号：US11477558
申请日：2006-06-30
申请人： Min-Joo Kim , Jong-Ho Lee , Sung-Kee Han , Hyung-Suk Jung
发明人： Min-Joo Kim , Jong-Ho Lee , Sung-Kee Han , Hyung-Suk Jung
IPC分类号： H01L29/94
CPC分类号： H01L21/823842 , H01L21/28194 , H01L29/4958 , H01L29/517 , H01L29/518 , H01L29/78
摘要： Disclosed are dual gate CMOS devices and methods for fabricating such devices. The dual gate structures are produced by forming a first gate electrode having first conductive stack on transistors of a first channel type and forming a second gate electrode having a second conductive stack on transistors of a second channel type, wherein the first and second conductive stacks have different compositions for including different work functions (Φ) in the respective transistors. At least one of the first and second conductive stacks will include metal(s) and/or metal compound(s) from which, when subjected to an appropriate thermal treatment, the metal(s) will diffuse to the interface formed between in the gate dielectric layer and the gate electrode and thereby modify the electrical properties of the associated transistors as reflected in, for example, a Vfb shift.
摘要翻译：公开了用于制造这种器件的双栅极CMOS器件和方法。双栅极结构通过在第一沟道型晶体管上形成具有第一导电叠层的第一栅极电极和在第二沟道型晶体管上形成具有第二导电叠层的第二栅极电极而制造，其中第一和第二导电叠层具有用于在各个晶体管中包括不同功函数（Phi）的不同组合。第一和第二导电叠层中的至少一个将包括金属和/或金属化合物，当经受适当的热处理时，金属将扩散到在栅极之间形成的界面电介质层和栅电极，从而改变相关晶体管的电性能，如例如V bias偏移所反映的。

9. 发明申请

US20060157796A1 Semiconductor device having dual gate electrode and related method of formation 审中-公开
标题翻译：具有双栅电极和相关的形成方法的半导体器件
公开(公告)号：US20060157796A1
公开(公告)日：2006-07-20
申请号：US11312806
申请日：2005-12-21
申请人： Min-Joo Kim , Jong-Ho Lee , Sung-Kee Han , Hyung-Suk Jung
发明人： Min-Joo Kim , Jong-Ho Lee , Sung-Kee Han , Hyung-Suk Jung
IPC分类号： H01L29/78 , H01L21/4763
CPC分类号： H01L21/823835 , H01L21/823842
摘要： A dual gate electrode semiconductor device and related method of formation are disclosed. The semiconductor device comprises a first gate electrode made of a metal silicide layer and a second gate electrode made of a metal layer, wherein the metal suicide is formed from the same metal as the metal layer.
摘要翻译：公开了一种双栅电极半导体器件及相关的形成方法。半导体器件包括由金属硅化物层制成的第一栅电极和由金属层制成的第二栅电极，其中金属硅化物由与金属层相同的金属形成。

10. 发明申请

US20080207274A1 METHOD AND APPARATUS FOR DISPLAYING EVENT OF MOBILE TERMINAL 有权
标题翻译：用于显示移动终端事件的方法和装置
公开(公告)号：US20080207274A1
公开(公告)日：2008-08-28
申请号：US12036378
申请日：2008-02-25
申请人： Min-Joo Kim
发明人： Min-Joo Kim
IPC分类号： H04B1/38
CPC分类号： H04M1/72544 , H04M1/72566 , H04M1/72572 , H04M1/72583 , H04M2250/22 , H04M2250/60
摘要： An event display apparatus and method of a mobile terminal are disclosed. The event display method of a mobile terminal includes: detecting events in the mobile terminal; displaying time graphics on a screen; and positioning the detected events on the time graph according to their types. Various scattered events in the mobile terminal are detected and displayed on the time graphics indicating time according to types of the detected events, so the events can be easily viewed and managed.
摘要翻译：公开了一种移动终端的事件显示装置和方法。移动终端的事件显示方法包括：检测移动终端中的事件; 在屏幕上显示时间图形; 并根据其类型将检测到的事件定位在时间图上。根据检测到的事件的类型，在指示时间的时间图形上检测并显示移动终端中的各种分散事件，因此可以容易地查看和管理事件。

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